KS8993F A5 Micrel Inc, KS8993F A5 Datasheet
KS8993F A5
Specifications of KS8993F A5
Related parts for KS8993F A5
KS8993F A5 Summary of contents
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General Description The Micrel KS8993F is the industry’s first single chip Fast Ethernet Media Converter with built-in OAM functions. The KS8993F integrates three MACs, two PHYs, OAM, frame buffer and high performance switch into a single chip ideal ...
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KS8993F Features (continued) • OAM Features: • Supports OAM sub-layer which conforms to TS-1000 specification from TTC (Telecommunication Technology Committee) • Sends and receives OAM frames to Center or Terminal side • Loop back mode to support loop back packet ...
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KS8993F Revision History Revision Date P0 1/14/03 P1 2/11/03 P2 4/1/03 P3 12/4/03 P4 3/11/04 P5 3/23/04 1.0 8/26/04 August 26, 2004 Summary of Changes Preliminary Information Added separate Link and activity on port 1 and port 2’s LED (pin ...
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KS8993F Table Of Contents 1 Signal Description .........................................................................................................................9 1.1 KS8993F Pin Diagram............................................................................................................................................................ 9 1.2 Pin Description and I/O Assignment..................................................................................................................................... 10 2 Functional Description ................................................................................................................20 2.1 Overview .............................................................................................................................................................................. 20 2.2 Media Converter Function .................................................................................................................................................... 20 2.2.1 OAM (Operations, Administration, and Management) ...
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KS8993F 4 Register Map: Switch, MC, & PHY (8 bits registers) ..................................................................50 4.1 Global Registers................................................................................................................................................................... 51 Register 0 (0x00): Chip ID0 ................................................................................................................................................. 51 Register 1 (0x01): Chip ID1 / Start Switch ........................................................................................................................... 51 Register 2 (0x02): Global Control 0 ..................................................................................................................................... ...
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KS8993F Register 89 (0x59): LNK Partner Status (2)......................................................................................................................... 74 Register 90 (0x5A): LNK Partner Vendor Info (1) ............................................................................................................... 74 Register 91 (0x5B): LNK Partner Vendor Info (2) ................................................................................................................ 74 Register 92 (0x5C): LNK Partner Vendor Info (3)................................................................................................................ 74 Register 93 ...
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KS8993F 8 Selection of Crystal/Oscillator .....................................................................................................98 9 Package Information ...................................................................................................................99 August 26, 2004 - 7 - Micrel Revision 1.0 ...
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KS8993F Table 1: FX and TX Mode Selection.................................................................................................................................................. 26 Table 2: MDI/MDI-X Pin Definition..................................................................................................................................................... 27 Table 3: MII Signals........................................................................................................................................................................... 35 Table 4: SNI (7-wire) Signals............................................................................................................................................................. 35 Table 5: MII Management Interface frame format.............................................................................................................................. 36 Table 6: Serial Management Interface (SMI) ...
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KS8993F 1 Signal Description 1.1 KS8993F Pin Diagram 103 PV32 104 PV21 105 PV23 106 DGND 107 VDDIO 108 PV12 109 PV13 110 P3_1PEN 111 P2_1PEN 112 P1_1PEN 113 P3_TXQ2 114 P2_TXQ2 115 P1_TXQ2 116 P3_PP 117 P2_PP 118 P1_PP ...
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KS8993F 1.2 Pin Description and I/O Assignment Pin # Pin Name Type 1 P1LED2 I(pu)/O 2 P1LED1 I(pu)/O 3 P1LED0 I(pu)/O 4 P2LED2 I(pu)/O 5 P2LED1 I(pu)/O 6 P2LED0 I(pu)/O 7 DGND Gnd 8 VDDIO Pwr August 26, 2004 Description ...
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KS8993F Pin # Pin Name Type 9 MCHS Ipd 10 MCCS Ipd 11 PDD# Ipu 12 ADVFC Ipu 13 P2ANEN Ipu 14 P2SPD Ipd 15 P2DPX Ipd 16 P2FFC Ipd 17 P1FST Opu 18 P1LCRCD Ipd August 26, 2004 Description ...
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KS8993F Pin # Pin Name Type 19 P1LPBM Ipd 20 P2LED3 Opd 21 DGND Gnd 22 VDDC / VOUT_1V8 Pwr 23 LEDSEL1 P1LED3 HWPOVR Ipd 28 P2MDIXDIS Ipd 29 P2MDIX ...
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KS8993F Pin # Pin Name Type 34 ML_EN Ipd 35 DIAGF Ipd 36 PWRDN I 37 AGND Gnd 38 VDDA Pwr 39 AGND Gnd 40 MUX1 I 41 MUX2 I 42 AGND Gnd 43 VDDA Pwr 44 FXSD1 I 45 ...
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KS8993F Pin # Pin Name Type 72 SMTXD3 Ipd 73 SMTXD2 Ipd 74 SMTXD1 Ipd 75 SMTXD0 Ipd 76 SMTXER Ipd 77 SMTXC Ipd/O 78 DGND Gnd 79 VDDIO Pwr 80 SMRXC Ipd/O 81 SMRXDV O 82 SMRXD3 Ipd/O 83 ...
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KS8993F Pin # Pin Name Type 93 PRSEL0 Ipd 94 MDC Ipu 95 MDIO Ipu/O 96 SPIQ Opu 97 SCL Ipu 98 SDA Ipu/O 99 SPIS_N Ipu 100 PS1 Ipd August 26, 2004 Description Priority Select Select queue servicing if ...
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KS8993F Pin # Pin Name Type 101 PS0 Ipd 102 PV31 Ipu 103 PV32 Ipu 104 PV21 Ipu 105 PV23 Ipu 106 DGND Gnd 107 VDDIO Pwr August 26, 2004 Description registers. [PS1, PS0] = [0, 0] --- I2C master ...
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KS8993F Pin # Pin Name Type 108 PV12 Ipu 109 PV13 Ipu 110 P3_1PEN Ipd 111 P2_1PEN Ipd 112 P1_1PEN Ipd 113 P3_TXQ2 Ipd 114 P2_TXQ2 Ipd 115 P1_TXQ2 Ipd 116 P3_PP Ipd August 26, 2004 Description Port 1 port ...
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KS8993F Pin # Pin Name Type 117 P2_PP Ipd 118 P1_PP Ipd 119 P3_TAGINS Ipd 120 P2_TAGINS Ipd 121 P1_TAGINS Ipd 122 DGND Gnd 123 VDDC Pwr 124 P3_TAGRM Ipd 125 P2_TAGRM Ipd 126 P1_TAGRM Ipd August 26, 2004 Description ...
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KS8993F Pin # Pin Name Type 127 TESTEN Ipd 128 SCANEN Ipd Note: Pwr = power supply; Gnd = ground input output; I/O = bi-directional Ipu = input w/ internal pull up; Ipd = input w/ ...
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KS8993F 2 Functional Description 2.1 Overview The KS8993F is a single-chip Fast Ethernet media converter. It contains two 10/100 physical layer transceivers, three MAC (Media Access Control) units, layer-2 managed switch, and frame buffer. On the media side, the KS8993F ...
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KS8993F Bit Command F0-F7 Preamble C0 Conservation Delimiter C1 Direction Delimiter C2-C3 Configuration Delimiter C4-C7 Version C8-C15 Control signal S0 Power S1 Optical S2 UTP link Way for information S5 Loop mode Terminal S6 option Terminal S7 ...
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KS8993F 2.2.2 MC (Media Converter) Mode MC (Media Converter) mode is selected and configured using hardware pins: MCCS and MCHS. Terminal MC mode without port 3 support is enabled when MCCS=0 and MCHS=1. In this mode, port 1 is 100BASE- ...
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KS8993F MC loop back operation is initiated and enabled by the center MC. The terminal MC provides the loop back path to return the loop back packet back to the center MC. In terminal MC mode, the KS8993F provides the ...
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KS8993F Pin Signal Name #27 HWPOVR 2.2.6 Port 1 LED Indicator Definition P1LED3 P1LED2 P1LED1 P1LED0 2.2.7 Port 2 LED Indicator Definition P2LED3 P2LED2 P2LED1 P2LED0 2.3 Physical Transceiver 2.3.1 100BASE-TX Transmit August 26, 2004 Type Description Input Hardware pin ...
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KS8993F The 100BASE-TX transmit function performs parallel to serial conversion, 4B/5B coding, scrambling, NRZ to NRZI conversion, MLT3 encoding and transmission. The circuit starts with a parallel to serial conversion, which converts the MII data from the MAC into a ...
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KS8993F FXSD1 (pin 44) Less than 0.2V Greater than 1V, but less than 1.8V Greater than 2.2V To ensure proper operation, a resistive voltage divider is recommended to adjust the fiber transceiver SD output voltage swing to match the KS8993F ...
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KS8993F The KS8993F supports auto MDI/MDI-X crossover. This facilitates the use of either a straight connection CAT-5 cable or a crossover CAT-5 cable. The auto-sense function will detect remote transmit and receive pairs, and correctly assign the transmit and receive ...
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KS8993F ...
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KS8993F 2.3.10 Auto Negotiation The KS8993F conforms to the auto negotiation protocol as described by the 802.3 committee. Auto negotiation allows UTP (Unshielded Twisted Pair) link partners to select the best common mode of operation. In auto negotiation the link ...
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KS8993F 1. The received packet's Source Address (SA) does not exist in the look up table. 2. The received packet is good, has no receiving errors, and is of legal length. The look up engine will insert the qualified Source ...
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KS8993F Figure 4: Destination Address look up flowchart, stage 1 PTF1 = NULL Search complete. Get PTF1 from Static MAC Table Search complete. Get PTF1 from Dynamic MAC Table August 26, 2004 Start NO VLAN ID valid? YES FOUND Search ...
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KS8993F Figure 5: Destination Address resolution flowchart, stage 2 August 26, 2004 PTF1 - RX Mirror Port Mirror - TX Mirror Process - Mirror - RX and TX Mirror Port VLAN Membership Check PTF2 - 32 - ...
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KS8993F The KS8993F will not forward the following packets: 1. Error packets. These include framing errors, FCS errors, alignment errors, and illegal size packet errors. 2. 802.3x pause frames. The KS8993F will intercept these packets and perform the appropriate actions. ...
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KS8993F On the transmit side, the KS8993F has intelligent and efficient means to determine when to invoke flow control. The flow control is based on the availability of system resources, including available buffers, available transmit queues and available receive queues. ...
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KS8993F device’s third MAC. The interface contains two distinct groups of signals: one for transmission and the other for reception. The following table describes the signals used in the MII interface. KS8993F PHY mode connections External MAC KS8993F PHY signals ...
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KS8993F Transmit enable Serial transmit data Transmit clock Collision detection Carrier sense Serial receive data Receive clock The SNI interface is a bit wide data interface and therefore runs at the network bit rate (not encoded). An additional signal on ...
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KS8993F The Serial Management Interface is the KS8993F non-standard MIIM interface that provides access to all KS8993F configuration registers. This interface allows an external device to completely monitor and control the states of the KS8993F. The SMI interface consists of ...
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KS8993F 1) “receive only” mirror on a port All the packets received on the port will be mirrored on the sniffer port. For example, port 1 is programmed to be “receive sniff” and port 3 is programmed to be the ...
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KS8993F DA found in Static MAC Use FID flag? Table? No Don’t care No Don’t care Yes Yes Yes Yes FID+SA found in Dynamic MAC Table? No Yes Advanced VLAN features, such as “Ingress VLAN filtering” and “Discard Non PVID ...
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KS8993F 1. “Transmit all high priority packets before low priority packets”, i.e. a low priority packet could be transmitted only when the high priority queue is empty; 2. “Transmit high priority packets and low priority packets at 10:1 ratio”, i.e. ...
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KS8993F the ingress port’s default tag. The default tags are programmed in register sets {19,20}, {35,36} and {51,52} for ports 1, 2 and 3, respectively. The KS8993F will not add tags to already tagged packets. Tag removal is enabled by ...
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KS8993F 2 2.10 Master Serial Bus Configuration 2 With an additional I C (“2-wire”) EEPROM, the KS8993F can perform more advanced switch features like “broadcast storm protection” and “rate control” without the need of an external processor. 2 ...
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KS8993F 2 2.10 Slave Serial Bus Configuration In managed mode, the KS8993F can be configured (external controller/CPU) has complete programming access to the KS8993F’s 128 registers. Programming access includes the Global Registers, Port Registers, Media ...
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KS8993F Similarly, SPI multiple write is initiated when the master device continues to drive the KS8993F SPIS_N input pin low after a byte (a register) is written. The KS8993F internal address counter will increment automatically to the next byte (next ...
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KS8993F The following four figures illustrate the SPI data cycles for “Write”, “Read”, “Multiple Write” and “Multiple Read”. The read data is registered out of SPIQ on the falling edge of SPIC, and the data input on SPID is registered ...
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KS8993F SPIS_N SPIC SPID X 0 SPIQ SPIS_N SPIC SPID SPIQ SPIS_N SPIC SPID X 0 SPIQ SPIS_N SPIC SPID SPIQ August 26, 2004 Figure 10: SPI Multiple Write 0 0 ...
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KS8993F 3 MII Management (MIIM) Registers The MIIM interface is used to access the MII PHY registers defined in this section. The SPI, I2C and SMI interfaces can also be used to access these registers. The latter three interfaces use ...
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KS8993F 15 T4 capable RO 14 100 Full RO capable 13 100 Half RO capable 12 10 Full RO capable 11 10 Half RO capable 10-7 Reserved RO 6 Preamble RO suppressed 5 AN complete RO 4 Far-End fault RO ...
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KS8993F Register 4: Auto-Negotiation Advertisement Ability Bit Name R/W 15 Next page RO 14 Reserved RO 13 Remote fault RO 12-11 Reserved RO 10 Pause R/W 9 Reserved R/W 8 Adv 100 Full R/W 7 Adv 100 Half R/W 6 ...
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KS8993F 4 Register Map: Switch, MC, & PHY (8 bits registers) Global Registers Register Register (Decimal) (Hex) 0-1 0x00 - 0x01 2-11 0x02 - 0x0B 12 0x0C 13-15 0x0D - 0x0F Port Registers Register Register (Decimal) (Hex) 16-29 0x10 – ...
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KS8993F 93 0x5D 94 0x5E 95 0x5F Advanced Control Registers Register Register (Decimal) (Hex) 96-103 0x60-0x67 104-109 0x68-0x6D 110-111 0x6E-0x6F 112-120 0x70-0x78 121-122 0x79-0x7A 123-124 0x7B-0x7C 125-126 0x7D-0x7E 127 0x7F 4.1 Global Registers Register 0 (0x00): Chip ID0 Bit Name ...
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KS8993F 3 Pass flow R/W control packet 2 Buffer share R/W mode 1 Reserved R/W 0 Link change R/W age Register 3 (0x03): Global Control 1 Bit Name R/W 7 Pass all R/W frames 6 Repeater R/W Mode 5 IEEE ...
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KS8993F Register 4 (0x04): Global Control 2 Bit Name R/W 7 Unicast R/W port-VLAN mismatch discard 6 Multicast R/W Storm protection Disable 5 Back R/W pressure mode 4 Flow control R/W and back pressure fair mode 3 No excessive R/W ...
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KS8993F 5 Reserved R/W 4 Reserved R/W 3-2 Priority R/W Scheme select 1 Reserved R/W 0 Sniff mode R./W select Register 6 (0x06): Global Control 4 Bit Name R/W 7 Reserved R/W 6 Switch MII R/W half duplex mode 5 ...
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KS8993F 3 Null VID R/W replacemen t 2-0 Broadcast R/W storm protection rate Bit [10:8] Register 7 (0x07): Global Control 5 Bit Name R/W 7-0 Broadcast R/W storm protection rate Bit [7:0] 100BT Rate: 148,800 frames/sec * 67 ms/interval * ...
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KS8993F 6 PHY power R/W save 5 CRC drop R/W 4 Reserved RW 3 MCLBM1 R/W 2 MCLBM0 R/W 1 LED mode R/W 0 Reserved R/W Register 12 (0x0C): Reserved Register Bit Name R/W 7-0 Reserved Register 13 (0x0D): User ...
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KS8993F Register 14 (0x0E): User Defined Register 2 Bit Name R/W 7-0 UDR2 R/W Register 15 (0x0F): User Defined Register 3 Bit Name R/W 7-0 UDR3 R/W 4.2 Port Registers The following registers are used to enable features that are ...
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KS8993F 1 Tag removal R/W 0 Priority R/W Enable Register 17 (0x11): Port 1 Control 1 Register 33 (0x21): Port 2 Control 1 Register 49 (0x31): Port 3 Control 1 Bit Name R/W 7 Sniffer port R/W 6 Receive sniff ...
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KS8993F 5 Discard Non R/W PVID packets 4 Force flow R/W control 3 Back R/W pressure enable 2 Transmit R/W enable 1 Receive R/W enable 0 Learning R/W disable Register 19 (0x13): Port 1 Control 3 Register 35 (0x23): Port ...
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KS8993F Bit Name R/W 7-0 Transmit high R/W priority rate control [7:0] Register 22 (0x16): Port 1 Control 6 Register 38 (0x26): Port 2 Control 6 Register 54 (0x36): Port 3 Control 6 Bit Name R/W 7-0 Transmit low R/W ...
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KS8993F Register 27 (0x1B): Port 1 Control 11 Register 43 (0x2B): Port 2 Control 11 Register 59 (0x3B): Port 3 Control 11 Bit Name R/W 7 Receive R/W differential priority rate control 6 Low priority R/W receive rate control enable ...
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KS8993F 6 Force R/W Speed 5 Force R/W duplex 4 Advertised R/W flow control capability 3 Advertised R/W 100BT Full duplex capability 2 Advertised R/W 100BT Half duplex capability 1 Advertised R/W 10BT Full duplex capability 0 Advertised R/W 10BT ...
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KS8993F 3 Power down R/W 2 Disable auto R/W MDI/MDI-X 1 Force MDI R/W 0 Reserve R/W Register 30 (0x1E): Port 1 Status 0 Register 46 (0x2E): Port 2 Status 0 Register 62 (0x3E): Reserved, not applied to port 3 ...
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KS8993F Register 31 (0x1F): Port 1 Status 1 Register 47 (0x2F): Port 2 Status 1 Register 63 (0x3F): Port 3 Status 1 Bit Name R/W 7 Reserved RO 6-5 Reserved RO 4 Receive flow RO control enable 3 Transmit flow ...
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KS8993F 4.3 Media Converter Registers Register 64 (0x40): PHY Address Bit Name R/W 7–5 Reserved RO 4 Addr4 R/W 3 Addr3 R/W 2 Addr2 R/W 1 Addr1 R/W 0 Addr0 R/W Register 65 (0x41): Center Side Status Bit Name R/W ...
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KS8993F Note: This register is managed by the Center side. Register 66 (0x42): Center Side Command Bit Name R/W Description 7–5 Timer R/W 000 = Reserved (Do Not Use) Delay 001 = 32us (default) 010 = 128us 011 = 256us ...
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KS8993F 4 SW reset R reset MC sub-layer, MACs of both PHY ports and switch fabric normal operation 3 Remote R enable “Remote Command” access at Center side and Terminal Command Enable 0 ...
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KS8993F Register 68 (0x44): Loop Back Setup1 Bit Name R/W Description 7 T7 R/W Center and Terminal sides 6 T6 R/W 0000_0000 : Clear valid transmit and valid receive counters in registers 4Dh R/W ...
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KS8993F Register 70 (0x46): Loop Back Result Counter for CRC Error Bit Name R/W Description 7 CRC7 RO Center side only 6 CRC6 RO This counter is incremented when loop back packet has CRC error. 5 CRC5 RO 4 CRC4 ...
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KS8993F Timeout 0 = normal operation 2 CMC Loop Center side is in Loop Back mode too long and the T1 timer has timeout. Back Timeout 0 = normal operation 1 Timeout Center side ...
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KS8993F Register 76 (0x4C): Remote Command 3 Bit Name R/W Description 7 AMM47 R/W If Center MC sends the “Remote Command” in register 0x42h, this register value will be used for M47-M40 of the Maintenance frame, instead of register 6 ...
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KS8993F Register 80 (0x50): My Status 1 (Terminal and Center side) Bit Name R/W Description H-MC Link speed H-MC Link Option 1 = Terminal MC mode 0 = Center MC mode 5 S5 ...
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KS8993F For Center MC mode, this bit is always “0” Full Duplex 0 = Half Duplex, or Register 0x50h bit[2] is “1” (UTP link is down For Terminal MC mode, this bit indicates the UTP ...
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KS8993F Register 88 (0x58): LNK Partner Status (1) Bit Name R/W 7-0 LS7–LS0 RO Register 89 (0x59): LNK Partner Status (2) Bit Name R/W 7-0 LS15–LS8 RO Register 90 (0x5A): LNK Partner Vendor Info (1) Bit Name R/W 7-0 LM7–LM0 ...
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KS8993F 4.4 Advanced Control Registers The IPv4 TOS priority control registers implement a fully decoded 64 bit DSCP (Differentiated Services Code Point) register used to determine priority from the 6 bit TOS field in the IP header. The most significant ...
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KS8993F Registers 104 to 109 define the switching engine’s MAC address. This 48-bit address is used as the source address for MAC pause control frames. Register 104 (0x68): MAC Address Register 0 Bit Name R/W 7-0 MACA[47:40] R/W Register 105 ...
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KS8993F Register 112 (0x70): Indirect Data Register 8 Bit Name R/W 68-64 Indirect data R/W Register 113 (0x71): Indirect Data Register 7 Bit Name R/W 63-56 Indirect data R/W Register 114 (0x72): Indirect Data Register 6 Bit Name R/W 55-48 ...
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KS8993F testing Register 123 (0x7B): Digital Testing Control 0 Bit Name R/W 7-0 Factory R/W testing Register 124 (0x7C): Digital Testing Control 1 Bit Name R/W 7-0 Factory R/W testing Register 125 (0x7D): Analog Testing Control 0 Bit Name R/W ...
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KS8993F Bit Name 57-54 FID 53 Use FID 52 Override 51 Valid 50-48 Forwarding ports 47-0 MAC address Examples: 1) Static Address Table Read (read the 2 Write to reg. 110 with 0x10 (read static table selected) Write to reg. ...
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KS8993F 4.6 VLAN Table VLAN table is used to do VLAN table look up. If 802.1Q VLAN mode is enabled (Register 5, Bit 7 = 1), this table will be used to retrieve the VLAN information that is associated with ...
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KS8993F 4.7 Dynamic MAC Address Table This table is read only. The table contents are maintained by KS8993F only. Bit Name 71 Data not ready 70-67 Reserved 66 MAC empty 65- valid entries 55-54 Time Stamp 53-52 Source ...
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KS8993F Bit Name 31 Reserve 30 Count Valid 29-0 Counter Values “Per Port” MIB Counters are read using indirect memory access. The base address offsets and address ranges for all three ports are: Port 1 : base is 0x00 and ...
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KS8993F 0xB RxBroadcast 0xC RxMulticast 0xD RxUnicast 0xE Rx64Octets 0xF Rx65to127Octets 0x10 Rx128to255Octets 0x11 Rx256to511Octets 0x12 Rx512to1023Octets 0x13 Rx1024to1522Octets 0x14 TxLoPriorityByte 0x15 TxHiPriorityByte 0x16 TxLateCollision 0x17 TxPausePkts 0x18 TxBroadcastPkts 0x19 TxMulticastPkts 0x1A TxUnicastPkts 0x1B TxDeferred 0x1C TxTotalCollision 0x1D TxExcessiveCollision 0x1E ...
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KS8993F 0x1F TxMultipleCollision Table 15: Format of “All Port Dropped Packet” MIB Counters Bit Name 30-16 Reserved 15-0 Counter values “All Port Dropped Packet” MIB Counters are read using indirect memory access. The address offsets for these counters are shown ...
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KS8993F Read reg. 120 (counter value 7-0) NOTES: 1. Both “Per Port” and “All Port Dropped Packet” MIB Counters do not indicate overflow. The application must keep track of overflow conditions for these counters. 2. “All Port Dropped Packet” MIB ...
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KS8993F 5 Electrical Specifications Stresses greater than those listed in this table may cause permanent damage to the device. Operation of the device at these or any other conditions above those specified in the operating sections of this specification is ...
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KS8993F 5.3 Electrical Characteristics Parameter Supply Current (including TX output driver current for KS8993F device only) 100BASE-TX operation (total) 100BASE- 10BASE-T operation (total) 10BASE 100BASE-TX (analog 100BASE-TX (digital 10BASE-T(analog 10BASE-T(digital) ...
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KS8993F Peak Differential Output V p Voltage Jitters Added Rise/Fall time 5.4 100BASE-FX Electrical Specification Parameter Sym Supply Current (including FX output driver current) 100BASE-FX operation - total 100BASE-FX (transmitter 100BASE-FX (analog 100BASE-FX (digital ...
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KS8993F 6 Timing Specifications 6.1 EEPROM Timing Receive Timing SCL SDA Transmit Timing SCL SDA Timing Description Parameter tcyc1 Clock cycle ts1 Setup time th1 tov1 Output Valid August 26, 2004 Figure 12: EEPROM Interface Input Timing Diagram ts1 tcyc1 ...
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KS8993F 6.2 SNI Timing Receive Timing MTXC MTXEN MTXD[0] Transmit Timing MRXC MRXDV MCOL MRXD[0] Timing Description Parameter tcyc2 Clock cycle ts2 Setup time th2 tov2 Output Valid August 26, 2004 Figure 14: SNI Input Timing Diagram ts2 tcyc2 Figure ...
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KS8993F 6.3 MII Timing 6.3.1 MAC Mode MII Timing Figure 16: MAC Mode MII Timing - Data received from MII Receive Timing MRXCLK MTXEN MTXER MTXD[3:0] Figure 17: MAC Mode MII Timing - Data transmitted to MII Transmit Timing MTXCLK ...
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KS8993F 6.3.2 PHY Mode MII Timing Figure 18: PHY Mode MII Timing – Data received from MII Receive Timing MTXCLK MTXEN MTXER MTXD[3:0] Figure 19: PHY Mode MII Timing - Data transmitted to MII Transmit Timing MRXCLK MRXDV MRXD[3:0] Timing ...
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KS8993F SPIS_N tCHSL SPIC tDVCH SPID SPIQ Timing Description Parameter fC Clock Frequency tCHSL SPIS_N Inactive Hold Time tSLCH SPIS_N Active Setup Time tCHSH SPIS_N Active Hold Time tSHCH SPIS_N Inactive Setup Time tSHSL SPIS_N Deselect Time tDVCH Data Input ...
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KS8993F SPIS_N SPIC SPIQ SPID Timing Description Parameter fC Clock Frequency tCLQX SPIQ Hold Time tCLQV Clock Low to SPIQ Valid tCH Clock High Time tCL Clock Low Time tQLQH SPIQ Rise Time tQHQL SPIQ Fall Time tSHQZ SPIQ Disable ...
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KS8993F 6.3.4 MDC/MDIO Timing Figure 22: MDC/MDIO Timing for MIIM and SMI Interfaces MDC MDIO (Into Chip) MDIO (Out of Chip) t MDC period P t MDC pulse width WL t MDC pulse width WH t MDIO Setup to MDC ...
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KS8993F 6.3.5 Auto Negotiation Timing TX+/TX- TX+/TX- t FLP burst to FLP burst BTB t FLP burst width FLPW t Clock/Data pulse width PW t Clock pulse to data pulse CTD t Clock pulse to clock pulse CTC Number of ...
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KS8993F Reset Timing 6.4 As long as the stable supply voltages to reset high timing (minimum of 10 ms) is met, there is no power sequencing requirement for the KS8993F supply voltages (1.8V, 3.3/2.5V). The reset timing requirement is summarized ...
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KS8993F 7 Selection of Isolation Transformer An 1:1 isolation transformer is required at the line interface. An isolation transformer with integrated common-mode choke is recommended for exceeding FCC requirements. characteristics. Parameter Turns Ratio Open-Circuit Inductance (min.) Leakage Inductance (max.) Inter-Winding ...
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KS8993F 9 Package Information Micrel is a registered trademark of Micrel and its subsidiaries in the United States and certain other countries. All other trademarks are the The information furnished by Micrel in this datasheet is believed to be accurate ...