KS8993F A5 Micrel Inc, KS8993F A5 Datasheet - Page 60

• Manufacturer Part Number: KS8993F A5
• Manufacturer: Micrel Inc

Specifications of KS8993F A5

• Number Of Primary Switch Ports: 3
• Internal Memory Buffer Size: 32
• Operating Supply Voltage (typ): 1.8/2.5/3.3V
• Fiber Support: Yes
• Integrated Led Drivers: Yes
• Phy/transceiver Interface: MII/SNI
• Power Supply Type: Analog/Digital
• Package Type: PQFP
• Data Rate (typ): 10/100Mbps
• Vlan Support: Yes
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Pin Count: 128
• Mounting: Surface Mount
• Jtag Support: No
• Operating Supply Voltage (max): 1.89/3.465V
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Not Compliant

KS8993F
Register 22 (0x16): Port 1 Control 6
Register 23 (0x17): Port 1 Control 7
Register 24 (0x18): Port 1 Control 8
Register 25 (0x19): Port 1 Control 9
Register 26 (0x1A): Port 1 Control 10
August 26, 2004
Bit
7-0
Bit
7-0
Bit
7-4
3-0
Bit
7-0
Bit
7-0
Bit
7-4
3-0
Register 38 (0x26): Port 2 Control 6
Register 54 (0x36): Port 3 Control 6
Register 39 (0x27): Port 2 Control 7
Register 55 (0x37): Port 3 Control 7
Register 40 (0x28): Port 2 Control 8
Register 56 (0x38): Port 3 Control 8
Register 41 (0x29): Port 2 Control 9
Register 57 (0x39): Port 3 Control 9
Register 42 (0x2A): Port 2 Control 10
Register 58 (0x3A): Port 3 Control 10
Name
Transmit high
priority rate
control [7:0]
Name
Transmit low
priority rate
control [7:0]
Name
Transmit low
priority rate
control [11:8]
Transmit high
priority rate
control [11:8]
Name
Receive high
priority rate
control [7:0]
Name
Receive low
priority rate
control [7:0]
Name
Receive low
priority rate
control [11:8]
Receive high
priority rate
control [11:8]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
This register along with port control 7, bits [3:0] form a 12-bits
field to determine how many “32Kbps” high priority blocks can
be transmitted. (in a unit of 4K bytes in a one second period).
Description
This register along with port control 7, bits [7:4] form a 12-bits
field to determine how many “32Kbps” low priority blocks can
be transmitted. (in a unit of 4K bytes in a one second period).
Description
These bits along with port control 6, bits [7:0] form a 12-bits
field to determine how many “32Kbps” low priority blocks can
be transmitted. (in a unit of 4K bytes in a one second period)
These bits along with port control 5, bits [7:0] form a 12-bits
field to determine how many “32Kbps” high priority blocks can
be transmitted. (in a unit of 4K bytes in a one second period)
Description
This register along with port control 10, bits [3:0] form a 12-
bits field to determine how many “32Kbps” high priority blocks
can be received. (in a unit of 4K bytes in a one second
period)
Description
This register along with port control 10, bits [7:4] form a 12-
bits field to determine how many “32Kbps” low priority blocks
can be received. (in a unit of 4K bytes in a one second
period)
Description
These bits along with port control 9, bits [7:0] form a 12-bits
field to determine how many “32Kbps” low priority blocks can
be received. (in a unit of 4K bytes in a one second period)
These bits along with port control 8, bits [7:0] form a 12-bits
field to determine how many “32Kbps” high priority blocks can
be received. (in a unit of 4K bytes in a one second period)
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Default
0x00
Default
0x00
Default
0x0
0x0
Default
0x00
Default
0x00
Default
0x0
0x0
Revision 1.0
Micrel