PN5120A0HN1/C1 NXP Semiconductors, PN5120A0HN1/C1 Datasheet - Page 73

• Manufacturer Part Number: PN5120A0HN1/C1
• Description: RF Wireless Misc COMBO ANALOG/DIGI IC
• Manufacturer: NXP Semiconductors
• Type: Transmission Moduler

Specifications of PN5120A0HN1/C1

• Package / Case: HVQFN EP
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 30 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PN5120A0HN1/C1,157

NXP Semiconductors
111334
Product data sheet
10.4.6 7-bit addressing
10.4.7 Register write access
During the I
to determine which slave will be selected by the master.
During device configuration, the designer has to ensure, that no collision with these
reserved addresses is possible. Check the corresponding I
list of reserved addresses.
For all PN512devices the upper 4 bits of the device bus address are reserved by NXP and
set to 0101(bin). The remaining 3 bits of the Slave Address can be freely configured in
order to prevent collisions with other I
Immediately after releasing the reset pin or after power on reset, the device defines the
I
taken for the upper 4 bits of the address. The lower 3 bits of the address are determined
by the logic levels on the pins D6 to D4. In case of a HIGH at EA, the address can be
completely specified at the external pins according to
detecting the different interface
latched immediately after releasing the reset condition. Further changes at the used pins
D6-D4 are not taken into consideration. Depending on the external wiring, the I
pins could be used for the output of test signals.
Remark: The PN512 in HVQFN32 package does not have a D0. In case of EA set to
HIGH, the I
To write data from the host controller via I
following frame format shall be used.
The first byte of a frame indicates the device address according to the I
second byte indicates the register address followed by up to n-data bytes. In one frame all
n-data bytes are written to the same register address. This enables for example a fast
FIFO access.
The read/write bit shall be set to logic 0.
2
Fig 22. First byte following the START procedure
C address according EA (pin A0). In case of a LOW at EA, the NXP reserved address is
2
2
C address bit 6 is fixed to 0.
C-bus addressing procedure the first byte after the START condition is used
Bit 6
Rev. 3.4 — 8 September 2009
Bit 5
Bit 4
types”. In both modes, the external address coding is
2
Bit 3
C devices used.
2
C to a specific register of the PN512 the
Bit 2
Table 139 “Connection scheme for
Bit 1
2
C specification for a complete
Bit 0
Transmission Module
© NXP B.V. 2010. All rights reserved.
2
C rules. The
PN512
2
C address
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