PN5120A0HN1/C1 NXP Semiconductors, PN5120A0HN1/C1 Datasheet - Page 102

• Manufacturer Part Number: PN5120A0HN1/C1
• Description: RF Wireless Misc COMBO ANALOG/DIGI IC
• Manufacturer: NXP Semiconductors
• Type: Transmission Moduler

Specifications of PN5120A0HN1/C1

• Package / Case: HVQFN EP
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 30 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PN5120A0HN1/C1,157

NXP Semiconductors
111334
Product data sheet
18.3.1.10 MFAuthent command
18.3.1.11 SoftReset Command
FeliCa (Card Operation mode):
The FeliCa polling command is finished and the command has automatically changed to
transceive. The FIFO contains the first command followed after the Polling by the FeliCa
protocol.The bit TargetActivated in the Status2Reg register is set to logic 1.
This command handles the MIFARE authentication in Reader/Writer mode to enable a
secure communication to any MIFARE card. The following data shall be written to the
FIFO before the command can be activated:
In total 12 bytes shall be written to the FIFO.
Note: When the MFAuthent command is active, any FIFO access is blocked. Anyhow if
there is an access to the FIFO, the bit WrErr in the ErrorReg register is set.
This command terminates automatically when the MIFARE card is authenticated and the
bit MFCrypto1On in the Status2Reg register is set to logic 1.
This command does not terminate automatically, when the card does not answer,
therefore the timer should be initialized to automatic mode. In this case, beside the bit
IdleIRq the bit TimerIRq can be used as termination criteria. During authentication
processing the bits RxIRq and TxIRq are blocked. The Crypto1On bit is only valid after
termination of the authent command (either after processing the protocol or after writing
IDLE to the command register).
In case there is an error during Authentication the bit ProtocolErr in the ErrorReg register
is set to logic 1 and the bit Crypto1On in register Status2Reg is set to logic 0.
This command performs a reset of the device. The configuration data of the internal buffer
remains unchanged. All registers are set to the reset values. This command terminates
automatically when finished.
Note: The SerialSpeedReg register is reset and therefore the serial data rate is set to
9.6 kbps.
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Authentication command code (60h, 61h)
Block address.
Sector key byte 0
Sector key byte 1
Sector key byte 2
Sector key byte 3
Sector key byte 4
Sector key byte 5
Card serial number byte 0
Card serial number byte 1
Card serial number byte 2
Card serial number byte 3
Rev. 3.4 — 8 September 2009
Transmission Module
© NXP B.V. 2010. All rights reserved.
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