TDA9885TS/V3 NXP Semiconductors, TDA9885TS/V3 Datasheet - Page 9

• Manufacturer Part Number: TDA9885TS/V3
• Description: Modulator / Demodulator ALIGN FRRE VIF/SIF CIR NEG MOD
• Manufacturer: NXP Semiconductors

Specifications of TDA9885TS/V3

• Package / Case: SSOP-24
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: - 20 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: TDA9885TS/V3,112

NXP Semiconductors
TDA9885_TDA9886_3
Product data sheet
8.3 VIF-AGC detector
8.4 FPLL detector
8.5 VCO and divider
Gain control is performed by sync level detection (negative modulation) or peak white
detection (positive modulation).
For negative modulation, the sync level voltage is stored at an integrated capacitor by
means of a fast peak detector. This voltage is compared with a reference voltage (nominal
sync level) by a comparator which charges or discharges the integrated AGC capacitor for
providing of the required VIF gain. The time constants for decreasing or increasing the
gain are nearly equal and the total AGC reaction time is fast to cope with ‘aeroplane
fluttering’.
For positive modulation, the white peak level voltage is compared with a reference voltage
(nominal white level) by a comparator which charges (fast) or discharges (slow) the
external AGC capacitor directly for providing the required VIF gain. The need of a very
long time constant for VIF gain increase is due to peak white level may appear only once
in a field. In order to reduce this time constant, an additional level detector increases the
discharging current of the AGC capacitor (fast mode) in the event of a decreasing VIF
amplitude step controlled by the detected actual black level voltage. The threshold level for
fast mode AGC is typically 6 dB video amplitude. The fast mode state is also transferred
to the SIF-AGC detector for speed-up. In case of missing peak white pulses, the VIF gain
increase is limited to typically +3 dB by comparing the detected actual black level voltage
with a corresponding reference voltage.
The VIF amplifier output signal is fed into a frequency detector and into a phase detector
via a limiting amplifier for removing the video AM.
During acquisition the frequency detector produces a current proportional to the
frequency difference between the VIF and the VCO signals. After frequency lock-in the
phase detector produces a current proportional to the phase difference between the VIF
and the VCO signals. The currents from the frequency and phase detectors are charged
into the loop filter which controls the VIF VCO and locks it to the frequency and phase of
the VIF carrier.
For a positive modulated VIF signal, the charging currents are optional gated by the
composite sync in order to avoid signal distortion in case of overmodulation. The gating
depth is switchable via the I
The VCO of the VIF FPLL operates as an integrated low radiation relaxation oscillator at
double the picture carrier frequency. The control voltage, required to tune the VCO to
double the picture carrier frequency, is generated at the loop filter by the frequency phase
detector. The possible frequency range is 50 MHz to 140 MHz (typical value).
The oscillator frequency is divided-by-two to provide two differential square wave signals
with exactly 90 degrees phase difference, independent of the frequency, for use in the
FPLL detectors, the video demodulator and the intercarrier mixer.
I
2
C-bus controlled multistandard alignment-free IF-PLL demodulators
Rev. 03 — 16 December 2008
2
C-bus.
TDA9885; TDA9886
© NXP B.V. 2008. All rights reserved.
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