ISP1506BBS,557 NXP Semiconductors, ISP1506BBS,557 Datasheet - Page 77

• Manufacturer Part Number: ISP1506BBS,557
• Description: RF Transceiver USB2.0 ULPI DDR OTG
• Manufacturer: NXP Semiconductors

Specifications of ISP1506BBS,557

• Operating Supply Voltage: 1.65 V to 3.6 V
• Mounting Style: SMD/SMT
• Package / Case: HVQFN-24
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935278349557 ISP1506BBS

NXP Semiconductors
24. Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10. RXCMD byte format . . . . . . . . . . . . . . . . . . . . .25
Table 11. LINESTATE[1:0] encoding for upstream
Table 12. LINESTATE[1:0] encoding for downstream
Table 13. Encoded V
Table 14. V
Table 15. Encoded USB event signals . . . . . . . . . . . . . .28
Table 16. PHY pipeline delays . . . . . . . . . . . . . . . . . . . . .32
Table 17. Link decision times . . . . . . . . . . . . . . . . . . . . .33
Table 18. Immediate register set overview . . . . . . . . . . .44
Table 19. Extended register set overview . . . . . . . . . . . .44
Table 20. Vendor ID Low register (address R = 00h)
Table 21. Vendor ID High register (address R = 01h)
Table 22. Product ID Low register (address R = 02h)
Table 23. Product ID High register (address R = 03h)
Table 24. Function Control register (address R = 04h
Table 25. Function Control register (address R = 04h
Table 26. Interface Control register (address R = 07h
Table 27. Interface Control register (address R = 07h
Table 28. OTG Control register (address R = 0Ah
Table 29. OTG Control register (address R = 0Ah
Table 30. USB Interrupt Enable Rising Edge register
Table 31. USB Interrupt Enable Rising Edge register
Table 32. USB Interrupt Enable Falling Edge register
ISP1506A_ISP1506B_2
Product data sheet
Ordering information . . . . . . . . . . . . . . . . . . . . .3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .5
Recommended charge pump capacitor value .12
ULPI signal description . . . . . . . . . . . . . . . . . .15
Signal mapping during low-power mode . . . . .16
Signal mapping for 3-pin serial mode . . . . . . .17
Operating states and their corresponding
resistor settings . . . . . . . . . . . . . . . . . . . . . . . .18
OTG Control register power control bits . . . . .24
TXCMD byte format . . . . . . . . . . . . . . . . . . . . .24
facing ports: peripheral . . . . . . . . . . . . . . . . . .26
facing ports: host . . . . . . . . . . . . . . . . . . . . . . .26
typical applications . . . . . . . . . . . . . . . . . . . . . .27
bit description . . . . . . . . . . . . . . . . . . . . . . . . .45
bit description . . . . . . . . . . . . . . . . . . . . . . . . .45
bit description . . . . . . . . . . . . . . . . . . . . . . . . .45
bit description . . . . . . . . . . . . . . . . . . . . . . . . .45
to 06h, W = 04h, S = 05h, C = 06h) bit
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
to 06h, W = 04h, S = 05h, C = 06h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
to 09h, W = 07h, S = 08h, C = 09h) bit
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
to 09h, W = 07h, S = 08h, C = 09h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
to 0Ch, W = 0Ah, S = 0Bh, C = 0Ch) bit
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
to 0Ch, W = 0Ah, S = 0Bh, C = 0Ch) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
(address R = 0Dh to 0Fh, W = 0Dh,
S = 0Eh, C = 0Fh) bit allocation . . . . . . . . . . . .48
(address R = 0Dh to 0Fh, W = 0Dh,
S = 0Eh, C = 0Fh) bit description . . . . . . . . . .49
BUS
indicators in RXCMD required for
BUS
voltage state . . . . . . . . . . . . . .26
Rev. 02 — 28 August 2008
Table 33. USB Interrupt Enable Falling Edge
Table 34. USB Interrupt Status register
Table 35. USB Interrupt Status register
Table 36. USB Interrupt Latch register
Table 37. USB Interrupt Latch register
Table 38. Debug register (address R = 15h) bit
Table 39. Debug register (address R = 15h) bit
Table 40. Scratch register (address R = 16h to 18h,
Table 41. Power Control register (address R = 3Dh
Table 42. Power Control register (address R = 3Dh
Table 43. Limiting values . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 44. Recommended operating conditions . . . . . . . . 54
Table 45. Static characteristics: supply pins . . . . . . . . . . 55
Table 46. Static characteristics: digital pins
Table 47. Static characteristics: digital pin FAULT . . . . . 56
Table 48. Static characteristics: analog I/O pins
Table 49. Static characteristics: charge pump . . . . . . . . 58
Table 50. Static characteristics: V
Table 51. Static characteristics: V
Table 52. Static characteristics: ID detection circuit . . . . 58
Table 53. Static characteristics: resistor reference . . . . . 59
Table 54. Dynamic characteristics: reset and clock . . . . 60
Table 55. Dynamic characteristics: digital I/O pins . . . . . 61
Table 56. Dynamic characteristics: analog I/O pins
Table 57. Recommended bill of materials . . . . . . . . . . . . 64
Table 58. SnPb eutectic process (from J-STD-020C) . . . 71
Table 59. Lead-free process (from J-STD-020C) . . . . . . 71
Table 60. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 61. Revision history . . . . . . . . . . . . . . . . . . . . . . . . 74
(address R = 10h to 12h, W = 10h,
S = 11h, C = 12h) bit allocation . . . . . . . . . . . . 49
register (address R = 10h to 12h,
W = 10h, S = 11h, C = 12h) bit description . . . 49
(address R = 13h) bit allocation . . . . . . . . . . . 50
(address R = 13h) bit description . . . . . . . . . . 50
(address R = 14h) bit allocation . . . . . . . . . . . 50
(address R = 14h) bit description . . . . . . . . . . 50
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
W = 16h, S = 17h, C = 18h) bit description . . . 51
to 3Fh, W = 3Dh, S = 3Eh, C = 3Fh) bit
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
to 3Fh, W = 3Dh, S = 3Eh, C = 3Fh) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
(CLOCK, DIR, STP, NXT, DATA[3:0],
RESET_N/PSW_N) . . . . . . . . . . . . . . . . . . . . . 55
(DP, DM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
(DP and DM) . . . . . . . . . . . . . . . . . . . . . . . . . . 61
ISP1506A; ISP1506B
ULPI HS USB OTG transceiver
BUS
BUS
comparators . . . . 58
resistors . . . . . . . . 58
© NXP B.V. 2008. All rights reserved.
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