ISP1506B NXP [NXP Semiconductors], ISP1506B Datasheet
ISP1506B
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ISP1506B Summary of contents
Page 1
... ISP1506A; ISP1506B ULPI Hi-Speed Universal Serial Bus On-The-Go transceiver Rev. 01 — 30 May 2007 1. General description The ISP1506 is a Universal Serial Bus (USB) On-The-Go (OTG) transceiver that is fully compliant with Supplement to the USB 2.0 Specification Rev. 1.2” (ULPI) Specification Rev. The ISP1506 can transmit and receive USB data at high-speed (480 Mbit/s), full-speed (12 Mbit/s) and low-speed (1 ...
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... N Supports 4-bit dual-edge data bus N Supports 60 MHz output clock configuration N Integrated Phase-Locked Loop (PLL), supporting one crystal or clock frequency: 19.2 MHz (ISP1506ABS) and 26 MHz (ISP1506BBS) N Fully programmable ULPI-compliant register set N Internal Power-On Reset (POR) circuit I Flexible system integration and very low current consumption, optimized for portable ...
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... MHz [1] ISP1506BBS 06B 26 MHz [1] The package marking is the first line of text on the IC package and can be used for IC identification. ISP1506A_ISP1506B_1 Product data sheet ISP1506A; ISP1506B Package Name Description HVQFN24 plastic thermal enhanced very thin quad flat package; no leads; 24 terminals; body 4 4 0.85 mm HVQFN24 plastic thermal enhanced very thin quad fl ...
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... MAP DRV V external BUS global POWER-ON reset RESET PLL CRYSTAL OSCILLATOR ISP1506 interface voltage internal power V REF VOLTAGE REGULATOR Rev. 01 — 30 May 2007 ISP1506A; ISP1506B ULPI HS USB OTG transceiver USB ATX TERMINATION 3 DM RESISTORS OTG MODULE DETECTOR V BUS COMPARATORS 10 V ...
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... FAULT (input) — Input pin for the external V signal If this pin is not used as either V BUS plain input tolerant 3.3 V regulator output crystal oscillator or clock input crystal oscillator output Rev. 01 — 30 May 2007 ISP1506A; ISP1506B ULPI HS USB OTG transceiver 18 NXT 17 STP 16 DIR 15 ...
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... PCB ground Section 7.9. Rev. 01 — 30 May 2007 ISP1506A; ISP1506B ULPI HS USB OTG transceiver power switch or external charge pump BUS . CC(I/O) Section 16. © ...
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... Product data sheet 1.1”. This interface must be connected to the USB link. charge pump or external source BUS monitoring, charging and discharging Rev. 01 — 30 May 2007 ISP1506A; ISP1506B ULPI HS USB OTG transceiver Ref. 3 “UTMI+ Low Pin Section 9. © NXP B.V. 2007. All rights reserved. ...
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... Resistors to temporarily charge and discharge V ISP1506A_ISP1506B_1 Product data sheet high-speed bus terminations on DP and DM for peripheral and host modes Section 16. comparators to determine the V Rev. 01 — 30 May 2007 ISP1506A; ISP1506B ULPI HS USB OTG transceiver Table 7. CC < 3 voltage level. This is required for the V BUS ...
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... First, the B-device makes sure that required between the C_A and C_B pins as shown in cp(C_A)-(C_B) Rev. 01 — 30 May 2007 ISP1506A; ISP1506B ULPI HS USB OTG transceiver . The downstream peripheral can draw its BUS valid comparator, session valid BUS voltage level ...
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... Product data sheet load. The value of C BUS V BUS ISP1506 C_B C_A 9. 16. V provides power to on-chip pads of the following pins: CC(I/O) Rev. 01 — 30 May 2007 ISP1506A; ISP1506B ULPI HS USB OTG transceiver depends on the cp(C_A)-(C_B) Section 7.9.7. OTG V BUS 0 cp(C_A)-(C_B) 004aaa600 , connected ...
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... ID pin dictates the initial role of the link detected as Table 3. For maximum efficiency, place capacitors as close as possible to pins. Section 16. ISP1506 Recommended charge pump capacitor value Rev. 01 — 30 May 2007 ISP1506A; ISP1506B ULPI HS USB OTG transceiver , must be connected between RREF RREF C_A C cp(C_A)-(C_B) C_B V ...
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... BUS fault events by sending RXCMDs on the ULPI bus. To use the FAULT pin, the link Section 16. . CC(I/O) Rev. 01 — 30 May 2007 ISP1506A; ISP1506B ULPI HS USB OTG transceiver 16. driving and monitoring. If neither function is used, Section 16. must not be attached when using the ISP1506 Section 16 ...
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... RXCMD is not 11b), it must disable the external BUS Ref. 3 “UTMI+ Low Pin Interface (ULPI) Specification 9.3.1. Ref. 3 “UTMI+ Low Pin Interface (ULPI) Specification Rev. 01 — 30 May 2007 ISP1506A; ISP1506B ULPI HS USB OTG transceiver . CC(I/O) 9.3. required when PSW_N is used. This pullup ...
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... ISP1506, except the charge pump. To ensure correct operation of the ISP1506, GND must be soldered to the cleanest ground available. ISP1506A_ISP1506B_1 Product data sheet ISP1506A; ISP1506B Ref. 3 “UTMI+ Low Pin Interface (ULPI) Specification Ref. 3 “UTMI+ Low Pin Interface (ULPI) 1.1”. Rev. 01 — 30 May 2007 ULPI HS USB OTG transceiver © ...
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... DATA[7:4], is transferred next on the falling edge of clock. Transferring an odd number of 4-bit nibbles is not allowed. Data lines have fixed direction and different meaning in low-power and 3-pin serial modes. ISP1506A_ISP1506B_1 Product data sheet ISP1506A; ISP1506B Section 15. A description of the ULPI pin behavior in Table 4. ...
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... LINESTATE1 directly driven by the analog receiver O reserved; the ISP1506 will drive this pin to LOW O active HIGH interrupt indication; will be asserted whenever any unmasked interrupt occurs Rev. 01 — 30 May 2007 ISP1506A; ISP1506B ULPI HS USB OTG transceiver supply (see Table 45). CC 1.1”. ...
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... The ISP1506 accommodates the various states summarizes operating states. The values of register settings in Table termination resistors on DP and DM Rev. 01 — 30 May 2007 ISP1506A; ISP1506B ULPI HS USB OTG transceiver 6. To enter 3-pin serial mode, the link sets the 1.1”. and Ref. 2 “On-The-Go Supplement 7. Resistor setting signals are defi ...
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... Rev. 01 — 30 May 2007 ISP1506A; ISP1506B ULPI HS USB OTG transceiver Internal resistor settings DM_PULL RPU_ RPD_ RPD_ DOWN DP_EN DP_EN DM_EN ...
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... Test K ISP1506A_ISP1506B_1 Product data sheet TERM OPMODE DP_PULL SELECT [1:0] DOWN 1b 00b 0b 1b 10b 0b 0b 10b 0b Rev. 01 — 30 May 2007 ISP1506A; ISP1506B ULPI HS USB OTG transceiver …continued Internal resistor settings DM_PULL RPU_ RPD_ RPD_ DOWN DP_EN DP_EN DM_EN ...
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... The internal POR pulse will also be generated whenever REG1V8 drops for more than t POR(trip) w(REG1V8_L PORP shows a typical start-up sequence. Rev. 01 — 30 May 2007 ISP1506A; ISP1506B ULPI HS USB OTG transceiver 1.0”. , for at least POR(trip) , and then rises above V POR(trip Figure 5 shows a possible curve of REG1V8. The ...
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... The link may start to detect DIR status level. If DIR is detected as LOW for three clock cycles, the link may send a RESET command. • The ULPI interface is ready for use. ISP1506A_ISP1506B_1 Product data sheet ISP1506A; ISP1506B Rev. 01 — 30 May 2007 ULPI HS USB OTG transceiver Figure 6. © NXP B.V. 2007. All rights reserved. ...
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... If the 19.2 MHz or 26 MHz clock is started before POR, the internal PLL startup(PLL) from POR. The CLOCK pin starts to output 60 MHz. The DIR pin will transition from HIGH to Rev. 01 — 30 May 2007 ISP1506A; ISP1506B ULPI HS USB OTG transceiver D RXCMD internal reset ...
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... Table 8 ISP1506A_ISP1506B_1 Product data sheet Hi-Z (link must drive) Hi-Z (link must drive) BUS summarizes settings to drive Rev. 01 — 30 May 2007 ISP1506A; ISP1506B ULPI HS USB OTG transceiver Figure 7 shows the ULPI . CC(I/O) Hi-Z (input) Hi-Z (input) . BUS © ...
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... Extended register read command (optional). The 8-bit address must be provided after the command is accepted. XX XXXXb REGR Register read command with 6-bit immediate address. Rev. 01 — 30 May 2007 ISP1506A; ISP1506B ULPI HS USB OTG transceiver power sources are disabled BUS charge pump is enabled BUS supply is enabled ...
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... RXCMD turnaround RXCMD shows the LINESTATE[1:0] encoding for upstream facing ports, which applies to Table 12 shows the LINESTATE[1:0] encoding for downstream facing ports, Rev. 01 — 30 May 2007 ISP1506A; ISP1506B ULPI HS USB OTG transceiver Figure 8. For details and diagrams, 1.1”. Section 9.5.2.1. state, see Section 9 ...
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... V V BUS A_VBUS_VLD and FAULT share the same pin and cannot be used simultaneously. BUS state encoding”. BUS Rev. 01 — 30 May 2007 ISP1506A; ISP1506B ULPI HS USB OTG transceiver squelch !squelch and HS_Differential_Receiver_Output !squelch and !HS_Differential_Receiver_Output invalid state are directly BUS ...
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... external circuit must be used to BUS sufficient level for operation. SESS_VLD must be enabled to detect the Rev. 01 — 30 May 2007 ISP1506A; ISP1506B ULPI HS USB OTG transceiver (0, X) RXCMD A_VBUS_VLD (1, 1) 004aaa752 The V state encoding is shown in BUS and take appropriate action ...
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... When the ISP1506 has detected a SYNC pattern on the USB bus, it signals an When the ISP1506 has detected an error while receiving a USB packet, it HostDisconnect is encoded into the RxEvent field of the RXCMD. Rev. 01 — 30 May 2007 ISP1506A; ISP1506B ULPI HS USB OTG transceiver Ref. 5 “USB 2.0 1.05”. HostDisconnect is 1.0” ...
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... TXCMD (EXTW (REGR) D extended immediate register write register read shows the sequence of events for USB reset and high-speed detection Table 12. Rev. 01 — 30 May 2007 ISP1506A; ISP1506B ULPI HS USB OTG transceiver Ref. 3 “UTMI+ Low TXCMD (EXTW extended register read Figure © ...
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... USB packets. For more information, refer to Rev. 1.1”. ISP1506A_ISP1506B_1 Product data sheet ISP1506A; ISP1506B . If the peripheral is in low-power mode, it must wake 0 Ref. 3 “UTMI+ Low Pin Interface (ULPI) Specification Rev. 01 — 30 May 2007 ULPI HS USB OTG transceiver © NXP B.V. 2007. All rights reserved. ...
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... K (10b) (00b) TXCMD NOPID K K ... (HS) 10 (chirp) squelch peripheral chirp K (10b) (00b) Rev. 01 — 30 May 2007 ISP1506A; ISP1506B ULPI HS USB OTG transceiver host chirp TXCMD TXCMD (REGW) NOPID K J ... K J host chirp K (10b) or chirp J (01b) RXCMDs TXCMD (REGW) ...
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... Table 17 for correct USB system operation. Examples of high-speed Rev. 01 — 30 May 2007 ISP1506A; ISP1506B ULPI HS USB OTG transceiver Figure 12. For details on USB ISP1506 ISP1506 ISP1506 asserts DIR, sends sends causing ...
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... Any subsequent transmission can occur after this time. USB interpacket delay (88 to 192 high-speed bit times) EOP link decision time ( clocks) Rev. 01 — 30 May 2007 ISP1506A; ISP1506B ULPI HS USB OTG transceiver IDLE TXCMD TX start delay (one to two clocks) © ...
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... Product data sheet USB interpacket delay (8 to 192 high-speed bit times) IDLE N turnaround link decision time ( clocks) Figure 15. Rev. 01 — 30 May 2007 ISP1506A; ISP1506B ULPI HS USB OTG transceiver TXCMD TX start delay (one to two clocks) © NXP B.V. 2007. All rights reserved. SYNC D0 D1 ...
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... PRE ID DP and DM timing is not to scale. illustrates how a host or a hub places a full-speed or low-speed peripheral into Figure 16 timing is not to scale, and does not show all RXCMD Rev. 01 — 30 May 2007 ISP1506A; ISP1506B ULPI HS USB OTG transceiver D1 D0 IDLE (min SYNC ...
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... RXCMD LINESTATE updates. ISP1506A_ISP1506B_1 Product data sheet resume K suspend TXCMD TXCMD (REGW) NOPID LINESTATE J LINESTATE K 00b J illustrates how a host or a hub places a high-speed enabled peripheral into Rev. 01 — 30 May 2007 ISP1506A; ISP1506B ULPI HS USB OTG transceiver EOP ... TXCMD 10b K SE0 J SE0 J 10b ...
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... The peripheral link sees terminations (TERMSELECT is set to 0b). The host link sets Rev. 01 — 30 May 2007 ISP1506A; ISP1506B ULPI HS USB OTG transceiver terminations, and enables the 1.5 k terminations (TERMSELECT is set to © NXP B.V. 2007. All rights reserved. ...
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... Product data sheet FS suspend TXCMD TXCMD (REGW) NOPID 01b 00b FS J (01b) LINESTATE J LINESTATE K 01b 00b FS J (01b) Rev. 01 — 30 May 2007 ISP1506A; ISP1506B ULPI HS USB OTG transceiver resume K HS idle TXCMD ... (REGW) 00b 10b 00b FS K (10b) squelch (00b) ...
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... SE0 of the EOP completes. This can be achieved by writing XCVRSELECT = 00b and TERMSELECT = 0b after LINESTATE indicates SE0. ISP1506A_ISP1506B_1 Product data sheet ISP1506A; ISP1506B Rev. 01 — 30 May 2007 ULPI HS USB OTG transceiver © NXP B.V. 2007. All rights reserved ...
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... TXCMD 00h REGW NOPID 01b (FS), 10b (LS) 10b TXCMD 00h NOPID 00b (HS), 01b (FS), 10b (LS) 10b Rev. 01 — 30 May 2007 ISP1506A; ISP1506B ULPI HS USB OTG transceiver TXCMD REGW 00b (HS only) 0b (HS only) 00b RXCMD TXCMD RXCMD RXCMD REGW Figure 19. The link must always send © ...
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... The following subsections describe how to use the ISP1506 OTG components. ISP1506A_ISP1506B_1 Product data sheet 00h 00h 80h PID 00h SYNC PID Ref. 1 “Universal Serial Bus Specification Rev. 2.0” BUS Rev. 01 — 30 May 2007 ISP1506A; ISP1506B ULPI HS USB OTG transceiver ... ... D FEh N DATA PAYLOAD EOP IDLE 004aaa893 © ...
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... V BUS B_SESS_END Ref. 2 “On-The-Go Supplement to the USB 2.0 Specification Rev. 1.1”, Section 3.10. provides an example of 3-pin serial mode. Rev. 01 — 30 May 2007 ISP1506A; ISP1506B ULPI HS USB OTG transceiver Section 7.6.4. When the controller is power by turning on the charge pump. BUS Section 9.4.1 and Section Ref. 2 “ ...
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... LOW and starts to immediately turn off its output drivers. The link senses the change of DIR from HIGH to LOW, but delays enabling its output buffers for one CLOCK cycle, avoiding data bus contention. ISP1506A_ISP1506B_1 Product data sheet ISP1506A; ISP1506B TRANSMIT DATA SYNC EOP Rev. 01 — ...
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... Size Address (6 bits) (bits) [1] [ 00h to 3Fh 8 40h to FFh Rev. 01 — 30 May 2007 ISP1506A; ISP1506B ULPI HS USB OTG transceiver References [3] [ Section 10.1.1 on page 05h 06h Section 10.1.2 on page 45 08h 09h Section 10.1.3 on page 46 ...
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... Value Description 15h Product ID High: Upper byte of the NXP product ID number; has a fixed value of 15h Table 24 RESET OPMODE[1: R/W/S/C R/W/S/C Rev. 01 — 30 May 2007 ISP1506A; ISP1506B ULPI HS USB OTG transceiver Table 21. Table 22. Table 23 TERM XCVRSELECT[1:0] SELECT R/W/S/C R/W/S/C R/W/S/C © ...
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... PROT_DIS THRU Reset 0 Access R/W/S/C R/W/S/C ISP1506A_ISP1506B_1 Product data sheet 7. Table IND_ reserved COMPL R/W/S/C R/W/S/C Rev. 01 — 30 May 2007 ISP1506A; ISP1506B ULPI HS USB OTG transceiver provides the bit allocation of the register CLOCK_ reserved 3PIN_ SUSPEND FSLS_ M SERIAL 0 0 R/W/S/C R/W/S/C R/W/S reserved 0 0 R/W/S/C © ...
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... V BUS Section Table 28 DRV_ CHRG_ VBUS VBUS R/W/S/C R/W/S/C Rev. 01 — 30 May 2007 ISP1506A; ISP1506B ULPI HS USB OTG transceiver /FAULT pin, not both. This bit must always be set to BUS 9.5.2. DISCHRG_ DM_PULL DP_PULL VBUS DOWN DOWN 0 1 R/W/S/C R/W/S/C R/W/S/C /FAULT pin ...
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... BUS Table 30 shows the bit allocation of the register ID_GND_R R/W/S/C R/W/S/C Rev. 01 — 30 May 2007 ISP1506A; ISP1506B ULPI HS USB OTG transceiver overcurrent indicator. BUS supply. Using an BUS . If DRV_VBUS_EXT is set to logic 1, then BUS pulsing SRP. The link must first BUS SESS_ ...
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... ID_GND_F R/W/S/C R/W/S/C Valid Fall: Enables interrupts and RXCMDs for logic 1 to logic 0 transitions on BUS Table 34) indicates the current value of the interrupt source signal. Rev. 01 — 30 May 2007 ISP1506A; ISP1506B ULPI HS USB OTG transceiver SESS_ SESS_ VBUS_ END_F VALID_F VALID_F 1 1 ...
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... R R Valid: Reflects the current value of the ID_GND_L Valid Latch: Automatically set when an unmasked event occurs on VBUS_VLD. Rev. 01 — 30 May 2007 ISP1506A; ISP1506B ULPI HS USB OTG transceiver SESS_ SESS_ VBUS_ END VALID VALID valid voltage comparator ...
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... Scratch: This is an empty register byte for testing purposes. Software can read, write, set and clear this register, and the functionality of the PHY will not be affected reserved R/W/S/C R/W/S/C Rev. 01 — 30 May 2007 ISP1506A; ISP1506B ULPI HS USB OTG transceiver Table 38. This register indicates the LINE STATE1 ...
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... Addresses 40h to FFh are not implemented. Operating on these addresses may result in undefined behavior of the PHY. ISP1506A_ISP1506B_1 Product data sheet ISP1506A; ISP1506B Rev. 01 — 30 May 2007 ULPI HS USB OTG transceiver © NXP B.V. 2007. All rights reserved ...
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... For details on the requirements for 1500 charge current discharge limit resistor resistance storage C S capacitor 100 pF Rev. 01 — 30 May 2007 ISP1506A; ISP1506B ULPI HS USB OTG transceiver and GND) have a BUS Figure Ref. 1 “Universal Serial Bus , see Section VBUS DEVICE UNDER TEST A B 0.1 F © ...
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... BUS I < all other pins; I < 0.5 V < V < +1 Conditions on pins CLOCK, STP, DATA[3:0] and RESET_N/PSW_N on pin V /FAULT BUS on pins DP, DM and ID on pin XTAL1 Rev. 01 — 30 May 2007 ISP1506A; ISP1506B ULPI HS USB OTG transceiver Min Max 0.5 +4.6 0.5 +2.5 0.5 V CC(I/O) 0.5 +6.0 0.5 +2.5 0.5 +4.6 [1] 0.5 +4.6 [2] 4 ...
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... ULPI interface pins are static = +85 C; unless otherwise specified. amb = 1 +25 C; unless otherwise specified. CC(I/O) amb Conditions CC(I/ Rev. 01 — 30 May 2007 ISP1506A; ISP1506B ULPI HS USB OTG transceiver Min Typ 3.0 3.3 1.65 1.8 1 210 - [ ...
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... C to +85 C; unless otherwise specified. amb = 1 +25 C; unless otherwise specified. CC(I/O) amb Conditions includes V range DI pull- pull-down on DP, DM GND L Rev. 01 — 30 May 2007 ISP1506A; ISP1506B ULPI HS USB OTG transceiver Min Typ Max 3 2 ...
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... C; unless otherwise specified. CC(I/O) amb Conditions for 1.5 k pull-up resistor includes V range DI pin to GND steady-state drive steady-state drive Rev. 01 — 30 May 2007 ISP1506A; ISP1506B ULPI HS USB OTG transceiver Min Typ Max 3.0 - 3.6 1425 1500 1575 100 - 150 525 - 625 300 ...
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... ID pin LOW and charge pump disabled ID pin HIGH or charge pump enabled = +85 C; unless otherwise specified. amb = 1 +25 C; unless otherwise specified. CC(I/O) amb Conditions ID_PULLUP is logic 1 Rev. 01 — 30 May 2007 ISP1506A; ISP1506B ULPI HS USB OTG transceiver Min Typ Max 4.65 5 ...
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... V O(VBUS) ( (mA) O(VBUS) Fig 23. V 004aaa878 I CC(cp) (mA) 3.4 3.5 3.6 V (V) CC(cp) Fig 25. Charge pump supply current as a function of Rev. 01 — 30 May 2007 ISP1506A; ISP1506B ULPI HS USB OTG transceiver Min Typ - 1.22 5. 3.3 V 3.0 V 5.00 4.50 4. O(VBUS) output voltage as a function of V BUS ...
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... XTAL1 only for square wave input only for square wave input only for square wave input measured from power good or assertion of pin STP Rev. 01 — 30 May 2007 ISP1506A; ISP1506B ULPI HS USB OTG transceiver Min Typ Max 0 ...
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... DM enabled excluding the first LR LF transition from the idle state DAT, SE0 to DP, DM; see Figure 27 DAT, SE0 to DP, DM; see Figure 27 Rev. 01 — 30 May 2007 ISP1506A; ISP1506B ULPI HS USB OTG transceiver Min Typ Max 3 5.0 4 ...
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... Fig 27. Timing of DAT and SE0 when transmitting to DP differential data lines 0 PHZ t PLZ V 0 logic output 004aaa574 Fig 29. Timing of DAT and SE0 when receiving from DP Rev. 01 — 30 May 2007 ISP1506A; ISP1506B ULPI HS USB OTG transceiver …continued Min Typ - - - - - - - - - - - - 0 ...
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... Fig 30. ULPI timing interface ISP1506A_ISP1506B_1 Product data sheet CLOCK t t su(STP) h(STP) (STP su(DATA) h(DATA) (8-BIT) (8-BIT) Rev. 01 — 30 May 2007 ISP1506A; ISP1506B ULPI HS USB OTG transceiver t , d(DIR) t d(NXT d(DIR d(DATA) d(NXT) © NXP B.V. 2007. All rights reserved. 004aaa722 ...
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... XTAL1 pin that has a DC offset [1] For detailed information, refer to application note ISP1506A_ISP1506B_1 Product data sheet ISP1506A; ISP1506B Value 0 mA), 270 nF (50 mA 470 nF (50 mA) 4 use a LOW ESR capacitor (0 for best performance 0 ...
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... USB MINI-AB GND RECEPTACLE IP4359CX4/LF SHIELD SHIELD 7 SHIELD 8 SHIELD 9 C VBUS (1) Frequency is version dependent: ISP1506A: 19.2 MHz; ISP1506B: 26 MHz. Fig 31. Using the ISP1506 with an OTG Controller; internal charge pump is utilized and crystal is attached V CC(I/ bypass CC(I/ RREF RREF ...
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... GND RECEPTACLE SHIELD 6 IP4359CX4/LF SHIELD ESD SHIELD 8 SHIELD 9 (1) Frequency is version dependent: ISP1506A: 19.2 MHz; ISP1506B: 26 MHz. Fig 32. Using the ISP1506 with an OTG Controller; external charge pump using ISP1506 internal CC(I/ OUT V CC(I/ RREF RREF ...
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... GND 4 IP4359CX4/LF SHIELD SHIELD 6 C VBUS C bypass (1) Frequency is version dependent: ISP1506A: 19.2 MHz; ISP1506B: 26 MHz. Fig 33. Using the ISP1506 with a standard USB Host Controller; external 5 V source with built-in FAULT and external square wave input on XTAL1 CC(I/O) C bypass V CC(I/ RREF ...
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... D+ 3 USB STANDARD-B RECEPTACLE GND SHIELD 5 IP4359CX4/ SHIELD 6 D ESD C bypass (1) Frequency is version dependent: ISP1506A: 19.2 MHz; ISP1506B: 26 MHz. Fig 34. Using the ISP1506 with a standard USB Peripheral Controller; external crystal is used CC(I/O) C bypass V CC(I/ RREF RREF ...
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... 2.5 scale (1) ( 4.1 2.25 4.1 2.25 0.5 2.5 3.9 1.95 3.9 1.95 REFERENCES JEDEC JEITA MO-220 - - - Rev. 01 — 30 May 2007 ISP1506A; ISP1506B ULPI HS USB OTG transceiver detail 0.5 2.5 0.1 0.05 0.05 0.1 0.3 EUROPEAN PROJECTION SOT616 ISSUE DATE ...
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... Solder bath specifications, including temperature and impurities ISP1506A_ISP1506B_1 Product data sheet ISP1506A; ISP1506B Rev. 01 — 30 May 2007 ULPI HS USB OTG transceiver © NXP B.V. 2007. All rights reserved ...
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... Lead-free process (from J-STD-020C) Package reflow temperature ( C) 3 Volume (mm ) < 350 260 260 250 Figure 36. Rev. 01 — 30 May 2007 ISP1506A; ISP1506B ULPI HS USB OTG transceiver Figure 36) than a PbSn process, thus 350 220 220 350 to 2000 > 2000 260 260 250 245 ...
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... International Electrotechnical Commission Low-Speed Non-Return-to-Zero Inverted On-The-Go [1] Physical Layer Packet Identifier Phase-Locked Loop Power-On Reset Receive Command Single-Ended Zero Rev. 01 — 30 May 2007 ISP1506A; ISP1506B ULPI HS USB OTG transceiver peak temperature 001aac844 © NXP B.V. 2007. All rights reserved. time ...
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... USB Implementers Forum UTMI+ Low Pin Interface USB 2.0 Transceiver Macrocell Interface USB 2.0 Transceiver Macrocell Interface Plus Data sheet status Product data sheet Rev. 01 — 30 May 2007 ISP1506A; ISP1506B ULPI HS USB OTG transceiver Change notice Supersedes - - © NXP B.V. 2007. All rights reserved. ...
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... Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. http://www.nxp.com salesaddresses@nxp.com Rev. 01 — 30 May 2007 ISP1506A; ISP1506B ULPI HS USB OTG transceiver © NXP B.V. 2007. All rights reserved ...
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... W = 0Ah 0Bh 0Ch) bit description . . . . . . . . . . . . . . . . . . . . . . . . .48 Table 30. USB Interrupt Enable Rising Edge register ISP1506A_ISP1506B_1 Product data sheet ISP1506A; ISP1506B (address R = 0Dh to 0Fh 0Dh 0Eh 0Fh) bit allocation . . . . . . . . . . . . . . . . . . . 48 Table 31. USB Interrupt Enable Rising Edge register (address R = 0Dh to 0Fh 0Dh 0Eh 0Fh) bit description . . . . . . . . . . . . . . . . . . 49 Table 32 ...
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... Table 57. Recommended bill of materials . . . . . . . . . . . .64 Table 58. SnPb eutectic process (from J-STD-020C .71 Table 59. Lead-free process (from J-STD-020C .71 Table 60. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . .72 Table 61. Revision history . . . . . . . . . . . . . . . . . . . . . . . .73 ISP1506A_ISP1506B_1 Product data sheet ISP1506A; ISP1506B Rev. 01 — 30 May 2007 ULPI HS USB OTG transceiver continued >> © NXP B.V. 2007. All rights reserved ...
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... Fig 31. Using the ISP1506 with an OTG Controller; internal charge pump is utilized and crystal is attached . . . . . . . . . . . . . . . . . . . . .65 Fig 32. Using the ISP1506 with an OTG Controller; ISP1506A_ISP1506B_1 Product data sheet ISP1506A; ISP1506B external charge pump using ISP1506 internal V valid and external square wave input BUS on XTAL1 Fig 33. Using the ISP1506 with a standard USB Host Controller ...
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... PSW_N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7.9.13 DIR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7.9.14 STP 7.9.15 NXT 7.9.16 CLOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.9.17 GND (die pad Modes of operation . . . . . . . . . . . . . . . . . . . . . 15 ISP1506A_ISP1506B_1 Product data sheet ISP1506A; ISP1506B 8.1 ULPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . 15 8.1.1 Synchronous mode . . . . . . . . . . . . . . . . . . . . 15 8.1.2 Low-power mode . . . . . . . . . . . . . . . . . . . . . . 16 8.1.3 3-pin full-speed or low-speed serial mode . . . 17 8.2 USB and OTG state transitions . . . . . . . . . . . 17 9 Protocol description . . . . . . . . . . . . . . . . . . . . 20 9.1 ULPI references . . . . . . . . . . . . . . . . . . . . . . . 20 9.2 Power-On Reset (POR ...
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... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2007. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Document identifier: ISP1506A_ISP1506B_1 All rights reserved. Date of release: 30 May 2007 ...