MT48H16M16LFBF-75:H TR Micron Technology Inc, MT48H16M16LFBF-75:H TR Datasheet - Page 65

• Manufacturer Part Number: MT48H16M16LFBF-75:H TR
• Description: DRAM Chip Mobile SDRAM 256M-Bit 16Mx16 1.8V 54-Pin VFBGA T/R
• Manufacturer: Micron Technology Inc
• Type: Mobile SDRAMr

Specifications of MT48H16M16LFBF-75:H TR

• Package: 54VFBGA
• Density: 256 Mb
• Address Bus Width: 15 Bit
• Operating Supply Voltage: 1.8 V
• Maximum Clock Rate: 133 MHz
• Maximum Random Access Time: 8|6 ns
• Operating Temperature: 0 to 70 °C

Figure 35: READ With Auto Precharge Interrupted by a READ
PDF: 09005aef834c13d2
256mb_mobile_sdram_y36n.pdf - Rev. I 11/09 EN
Internal
states
Command
Note:
Address
Bank m
Bank n
CLK
DQ
WRITE with auto precharge interrupted by a WRITE (with or without auto precharge)
A WRITE to bank m will interrupt a WRITE on bank n when registered. The precharge to
bank n will begin after
registered. The last valid data WRITE to bank n will be data registered one clock prior to
a WRITE to bank m (see Figure 42 (page 71)).
1. DQM is LOW.
Page active
NOP
T0
READ - AP
Page active
Bank n,
Bank n
T1
Col a
READ with burst of 4
256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM
t
WR is met, where
T2
CL = 3 (bank n)
NOP
65
READ - AP
Bank m,
T3
Bank m
Col d
Interrupt burst, precharge
READ with burst of 4
Micron Technology, Inc. reserves the right to change products or specifications without notice.
t
T4
WR begins when the WRITE to bank m is
CL = 3 (bank m)
NOP
t
RP - bank n
D
OUT
T5
NOP
D
OUT
PRECHARGE Operation
T6
NOP
D
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OUT
Idle
T7
Don’t Care
NOP
t RP - bank m
D
Precharge
OUT