MT48H16M16LFBF-75:H TR Micron Technology Inc, MT48H16M16LFBF-75:H TR Datasheet - Page 30
MT48H16M16LFBF-75:H TR
Manufacturer Part Number
MT48H16M16LFBF-75:H TR
Description
DRAM Chip Mobile SDRAM 256M-Bit 16Mx16 1.8V 54-Pin VFBGA T/R
Manufacturer
Micron Technology Inc
Type
Mobile SDRAMr
Datasheet
1.MT48H8M32LFB5-6H.pdf
(86 pages)
Specifications of MT48H16M16LFBF-75:H TR
Package
54VFBGA
Density
256 Mb
Address Bus Width
15 Bit
Operating Supply Voltage
1.8 V
Maximum Clock Rate
133 MHz
Maximum Random Access Time
8|6 ns
Operating Temperature
0 to 70 °C
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- Download datasheet (3Mb)
WRITE
Figure 10: WRITE Command
PDF: 09005aef834c13d2
256mb_mobile_sdram_y36n.pdf - Rev. I 11/09 EN
Note:
The WRITE command is used to initiate a burst write access to an active row. The val-
ues on the BA0 and BA1 inputs select the bank; the address provided selects the starting
column location. The value on input A10 determines whether auto precharge is used. If
auto precharge is selected, the row being accessed is precharged at the end of the write
burst; if auto precharge is not selected, the row remains open for subsequent accesses.
Input data appearing on the DQ is written to the memory array, subject to the DQM
input logic level appearing coincident with the data. If a given DQM signal is registered
LOW, the corresponding data is written to memory; if the DQM signal is registered
HIGH, the corresponding data inputs are ignored and a WRITE is not executed to that
byte/column location.
BA0, BA1
Address
1. EN AP = enable auto precharge, DIS AP = disable auto precharge.
RAS#
CAS#
A10
WE#
CKE
CLK
CS#
1
HIGH
Valid address
256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM
Column address
Bank address
DIS AP
EN AP
30
Don’t Care
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©2008 Micron Technology, Inc. All rights reserved.
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