LAN9311I-NZW Standard Microsystem (Smsc), LAN9311I-NZW Datasheet - Page 82

• Manufacturer Part Number: LAN9311I-NZW
• Manufacturer: Standard Microsystem (Smsc)

Specifications of LAN9311I-NZW

• Package: 128XVTQFP
• Phy/transceiver Interface: MII
• Number Of Primary Switch Ports: 2
• Maximum Data Rate: 100 Mbps
• Internal Memory Buffer Size: 32 KB
• Vlan Support: Yes
• Power Supply Type: Analog
• Minimum Single Supply Voltage: 3 V
• Maximum Single Supply Voltage: 3.6 V
• Maximum Supply Current: 0.295 A
• Maximum Power Dissipation: 1070 mW

Chapter 7 Ethernet PHYs
Revision 1.7 (06-29-10)
7.1
7.1.1
PHY_ADDR_SEL_STRAP
The LAN9311/LAN9311i contains three PHYs: Port 1 PHY, Port 2 PHY and a Virtual PHY. The Port 1
& 2 PHYs are identical in functionality and each connect their corresponding Ethernet signal pins to
the switch fabric MAC of their respective port. These PHYs interface with their respective MAC via an
internal MII interface. The Virtual PHY provides the virtual functionality of a PHY and allows connection
of the Host MAC to port 0 of the switch fabric as if it was connected to a single port PHY. All PHYs
comply with the IEEE 802.3 Physical Layer for Twisted Pair Ethernet and can be configured for full/half
duplex 100 Mbps (100BASE-TX) or 10Mbps (10BASE-T) Ethernet operation. All PHY registers follow
the IEEE 802.3 (clause 22.2.4) specified MII management register set and can be configured indirectly
via the Host MAC, or directly via the memory mapped Virtual PHY registers. Refer to
"Ethernet PHY Control and Status Registers"
The LAN9311/LAN9311i Ethernet PHYs are discussed in detail in the following sections:
PHY Addressing
Each individual PHY is assigned a unique default PHY address via the phy_addr_sel_strap
configuration strap as shown in
be changed via the
(PHY_SPECIAL_MODES_x). For proper operation, all LAN9311/LAN9311i PHY addresses must be
unique. No check is performed to assure each PHY is set to a different address. Configuration strap
values are latched upon the de-assertion of a chip-level reset as described in
"Configuration Straps," on page
Functional Overview
0
1
Section 7.2, "Port 1 & 2 PHYs," on page 83
Section 7.3, "Virtual PHY," on page 96
VIRTUAL PHY DEFAULT
Table 7.1 Default PHY Serial MII Addressing
ADDRESS VALUE
PHY Address (PHYADD)
0
1
Table
40.
DATASHEET
7.1. In addition, the Port 1 PHY and Port 2 PHY addresses can
82
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
for details on the Ethernet PHY registers.
PORT 1 PHY DEFAULT
field in the
ADDRESS VALUE
1
2
Port x PHY Special Modes Register
PORT 2 PHY DEFAULT
ADDRESS VALUE
SMSC LAN9311/LAN9311i
Section 4.2.4,
2
3
Section 14.4,
Datasheet