LAN9311I-NZW Standard Microsystem (Smsc), LAN9311I-NZW Datasheet - Page 137

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LAN9311I-NZW

Manufacturer Part Number
LAN9311I-NZW
Description
Manufacturer
Standard Microsystem (Smsc)
Datasheet

Specifications of LAN9311I-NZW

Package
128XVTQFP
Phy/transceiver Interface
MII
Number Of Primary Switch Ports
2
Maximum Data Rate
100 Mbps
Internal Memory Buffer Size
32 KB
Vlan Support
Yes
Power Supply Type
Analog
Minimum Single Supply Voltage
3 V
Maximum Single Supply Voltage
3.6 V
Maximum Supply Current
0.295 A
Maximum Power Dissipation
1070 mW

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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9311/LAN9311i
9.9.4
9.9.5
Stopping and Starting the Receiver
To stop the receiver, the host must clear the RXEN bit in the
When the receiver is halted, the RXSTOP_INT will be pulsed and reflected in the
Register
The host must re-enable the receiver by setting the RXEN bit.
Receiver Errors
If the Receiver Error (RXE) flag is asserted in the
the receiver will continue operation. RX Error (RXE) will be asserted under the following conditions:
It is the duty of the host to identify and resolve any error conditions.
A host underrun of RX Data FIFO
A host underrun of the RX Status FIFO
An overrun of the RX Status FIFO
(INT_STS). Once stopped, the host can optionally clear the RX Status and RX Data FIFOs.
DATASHEET
137
Interrupt Status Register (INT_STS)
Host MAC Control Register
Revision 1.7 (06-29-10)
Interrupt Status
for any reason,
(HMAC_CR).

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