LAN9303-ABZJ Standard Microsystem (Smsc), LAN9303-ABZJ Datasheet - Page 26

• Manufacturer Part Number: LAN9303-ABZJ
• Description: Ethernet Switch 3-Port 10Mbps/100Mbps 56-Pin QFN EP
• Manufacturer: Standard Microsystem (Smsc)

Specifications of LAN9303-ABZJ

• Package: 56QFN EP
• Phy/transceiver Interface: MII/RMII
• Number Of Primary Switch Ports: 3
• Maximum Data Rate: 100 Mbps
• Vlan Support: Yes
• Power Supply Type: Analog
• Minimum Single Supply Voltage: 3 V
• Maximum Single Supply Voltage: 3.6 V
• Maximum Supply Current: 0.19(Typ) A

Revision 1.4 (07-07-10)
PINS
NUM
1
1
1
1
Port 0 MII Input
Port 0 MII Input
Port 0 MII Input
Port 0 MII Input
Data Valid
NAME
Data 2
Data 1
Data 0
SYMBOL
P0_INDV
P0_IND2
P0_IND1
P0_IND0
Table 3.4 Port 0 MII/RMII Pins (continued)
Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII
DATASHEET
BUFFER
TYPE
(PD)
(PD)
(PD)
(PD)
(PD)
(PD)
(PD)
(PD)
(PD)
(PD)
(PD)
IS
IS
IS
IS
IS
IS
IS
IS
IS
IS
IS
-
26
MII MAC Mode: This pin is the receive data 2 bit
from the external PHY to the switch.
MII PHY Mode: This pin is transmit data 2 bit from
the external MAC to the switch. The pull-down and
input buffer are disabled when the
(VPHY_ISO)
Control Register
RMII PHY Mode: This pin is not used.
MII MAC Mode: This pin is the receive data 1 bit
from the external PHY to the switch.
MII PHY Mode: This pin is the transmit data 1 bit
from the external MAC to the switch. The pull-down
and input buffer are disabled when the
(VPHY_ISO)
Control Register
RMII PHY Mode: This pin is the transmit data 1 bit
from the external MAC to the switch. The pull-down
and input buffer are disabled when the
(VPHY_ISO)
Control Register
MII MAC Mode: This pin is the receive data 0 bit
from the external PHY to the switch.
MII PHY Mode: This pin is the transmit data 0 bit
from the external MAC to the switch. The pull-down
and input buffer are disabled when the
(VPHY_ISO)
Control Register
RMII PHY Mode: This pin is the transmit data 0 bit
from the external MAC to the switch. The pull-down
and input buffer are disabled when the
(VPHY_ISO)
Control Register
MII MAC Mode: This pin is the RX_DV signal from
the external PHY and indicates valid data on
P0_IND[3:0] and P0_INER.
MII PHY Mode: This pin is the TX_EN signal from
the external MAC and indicates valid data on
P0_IND[3:0] and P0_INER. The pull-down and
input buffer are disabled when the
(VPHY_ISO)
Control Register
RMII PHY Mode: This pin is the TX_EN signal from
the external MAC and indicates valid data on
P0_IND[1:0]. The pull-down and input buffer are
disabled when the
the
(VPHY_BASIC_CTRL).
Virtual PHY Basic Control Register
bit is set in the
bit is set in the
bit is set in the
bit is set in the
bit is set in the
bit is set in the
(VPHY_BASIC_CTRL).
(VPHY_BASIC_CTRL).
(VPHY_BASIC_CTRL).
(VPHY_BASIC_CTRL).
(VPHY_BASIC_CTRL).
(VPHY_BASIC_CTRL).
DESCRIPTION
Isolate (VPHY_ISO)
SMSC LAN9303/LAN9303i
Virtual PHY Basic
Virtual PHY Basic
Virtual PHY Basic
Virtual PHY Basic
Virtual PHY Basic
Virtual PHY Basic
Isolate
Isolate
bit is set in
Isolate
Isolate
Isolate
Isolate
Datasheet