LAN9303-ABZJ Standard Microsystem (Smsc), LAN9303-ABZJ Datasheet - Page 170
LAN9303-ABZJ
Manufacturer Part Number
LAN9303-ABZJ
Description
Ethernet Switch 3-Port 10Mbps/100Mbps 56-Pin QFN EP
Manufacturer
Standard Microsystem (Smsc)
Datasheet
1.LAN9303-ABZJ.pdf
(367 pages)
Specifications of LAN9303-ABZJ
Package
56QFN EP
Phy/transceiver Interface
MII/RMII
Number Of Primary Switch Ports
3
Maximum Data Rate
100 Mbps
Vlan Support
Yes
Power Supply Type
Analog
Minimum Single Supply Voltage
3 V
Maximum Single Supply Voltage
3.6 V
Maximum Supply Current
0.19(Typ) A
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LAN9303-ABZJ
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
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Revision 1.4 (07-07-10)
13.2.6.1
31:16
BITS
15
14
13
12
11
10
9
RESERVED
(See
Reset (VPHY_RST)
When set, this bit resets all the Virtual PHY registers to their default state.
This bit is self clearing.
0: Normal Operation
1: Reset
Loopback (VPHY_LOOPBACK)
This bit enables/disables the loopback mode. When enabled, transmissions
from the external MAC are not sent to the Switch Fabric. Instead, they are
looped back onto the receive path.
0: Loopback mode disabled (normal operation)
1: Loopback mode enabled
Speed Select LSB (VPHY_SPEED_SEL_LSB)
This bit is used to set the speed of the Virtual PHY when the
Negotiation (VPHY_AN)
0: 10 Mbps
1: 100/200 Mbps
Auto-Negotiation (VPHY_AN)
This bit enables/disables Auto-Negotiation. When enabled, the
LSB (VPHY_SPEED_SEL_LSB)
are overridden.
0: Auto-Negotiation disabled
1: Auto-Negotiation enabled
Power Down (VPHY_PWR_DWN)
This bit is not used by the Virtual PHY and has no effect.
Isolate (VPHY_ISO)
This bit controls the MII input/output pins. When set and in MII/RMII PHY
mode, the MII output pins are not driven, MII pull-ups and pull-downs are
disabled and the input pins are ignored. When in MAC mode, this bit is
ignored and has no effect.
0: Non-Isolated (Normal operation)
1: Isolated
Restart Auto-Negotiation (VPHY_RST_AN)
When set, this bit updates the emulated Auto-Negotiation results.
0: Normal operation
1: Auto-Negotiation restarted
Virtual PHY Basic Control Register (VPHY_BASIC_CTRL)
This read/write register is used to configure the Virtual PHY.
Note: This register is re-written in its entirety by the EEPROM Loader following the release or reset
Note
or a RELOAD command. Refer to
information.
13.17)
Offset:
Index (decimal):
bit is disabled.
(Note
1C0h
0
DESCRIPTION
Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII
and
13.18)
Duplex Mode (VPHY_DUPLEX)
DATASHEET
170
Section 8.4, "EEPROM Loader," on page 113
Size:
Speed Select
Auto-
32 bits
bits
TYPE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
SMSC LAN9303/LAN9303i
RO
SC
SC
DEFAULT
Datasheet
0b
0b
0b
1b
0b
0b
0b
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