LAN9303-ABZJ Standard Microsystem (Smsc), LAN9303-ABZJ Datasheet - Page 154

• Manufacturer Part Number: LAN9303-ABZJ
• Description: Ethernet Switch 3-Port 10Mbps/100Mbps 56-Pin QFN EP
• Manufacturer: Standard Microsystem (Smsc)

Specifications of LAN9303-ABZJ

• Package: 56QFN EP
• Phy/transceiver Interface: MII/RMII
• Number Of Primary Switch Ports: 3
• Maximum Data Rate: 100 Mbps
• Vlan Support: Yes
• Power Supply Type: Analog
• Minimum Single Supply Voltage: 3 V
• Maximum Single Supply Voltage: 3.6 V
• Maximum Supply Current: 0.19(Typ) A

Revision 1.4 (07-07-10)
13.2.4.2
BITS
31:7
6
5
4
3
2
1
RESERVED
Port 2 Backpressure Enable (BP_EN_2)
This bit enables/disables the generation of half-duplex backpressure on
switch Port 2.
0: Disable backpressure
1: Enable backpressure
Port 2 Current Duplex (CUR_DUP_2)
This bit indicates the actual duplex setting of switch Port 2.
0: Full-Duplex
1: Half-Duplex
Port 2 Current Receive Flow Control Enable (CUR_RX_FC_2)
This bit indicates the actual receive flow setting of switch Port 2.
0: Flow control receive is currently disabled
1: Flow control receive is currently enabled
Port 2 Current Transmit Flow Control Enable (CUR_TX_FC_2)
This bit indicates the actual transmit flow setting of switch Port 2.
0: Flow control transmit is currently disabled
1: Flow control transmit is currently enabled
Port 2 Full-Duplex Receive Flow Control Enable (RX_FC_2)
When the MANUAL_FC_2 bit is set, or Auto-Negotiation is disabled, this bit
enables/disables the detection of full-duplex Pause packets on switch Port 2.
0: Disable flow control receive
1: Enable flow control receive
Port 2 Full-Duplex Transmit Flow Control Enable (TX_FC_2)
When the MANUAL_FC_2 bit is set, or Auto-Negotiation is disabled, this bit
enables/disables full-duplex Pause packets to be generated on switch Port
2.
0: Disable flow control transmit
1: Enable flow control transmit
Port 2 Manual Flow Control Register (MANUAL_FC_2)
This read/write register allows for the manual configuration of the switch Port 2 flow control. This
register also provides read back of the currently enabled flow control settings, whether set manually
or Auto-Negotiated. Refer to
information.
Note: The flow control values in the PHY_AN_ADV_2 register (see
within the PHY are not affected by the values of this register.
Offset:
1A4h
DESCRIPTION
Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII
Section 6.2.3, "Flow Control Enable Logic," on page 62
DATASHEET
154
Size:
32 bits
Section 13.3.2.5, on page
TYPE
R/W
R/W
R/W
SMSC LAN9303/LAN9303i
RO
RO
RO
RO
Note 13.10
Note 13.10
for additional
DEFAULT
Note 13.8
Note 13.9
Note 13.9
Note 13.9
Datasheet
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199)