AD5748ACPZ Analog Devices Inc, AD5748ACPZ Datasheet - Page 7

• Manufacturer Part Number: AD5748ACPZ
• Description: ZDPLC +/-24V DRIVER
• Manufacturer: Analog Devices Inc

Specifications of AD5748ACPZ

• Amplifier Type: Instrumentation
• Number Of Circuits: 1
• Slew Rate: 2 V/µs
• Current - Output / Channel: 15mA
• Voltage - Supply, Single/dual (±): ±12 V ~ 24 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: *
• No. Of Amplifiers: 3
• Supply Voltage Range: ± 12V To ± 24V
• Supply Current: 5.2mA
• Amplifier Case Style: LFCSP
• No. Of Pins: 32
• Operating Temperature Range: -40°C To +105°C
• Svhc: No
• Rohs Compliant: Yes
• Bandwidth: 100kHz
• Amplifier Output: Differential
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Output Type: -
• Gain Bandwidth Product: -
• -3db Bandwidth: -
• Current - Input Bias: -
• Voltage - Input Offset: -
• Current - Supply: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TIMING CHARACTERISTICS
AV
300 Ω. All specifications T
Table 3.
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
1
2
1
2
3
4
5
6
7
8
9
11
12
13
Guaranteed by characterization, but not production tested.
All input signals are specified with t
, t
DD
10
/AV
SS
1, 2
= ±12 V (± 10%) to ±24 V (± 10%), DVCC = 2.7 V to 5.5 V, GND = 0 V. VOUT: R
Limit at T
20
8
8
5
10
5
5
5
1.5
5
40
10
MIN
MIN
to T
, T
R
= t
MAX
F
MAX
= 5 ns (10% to 90% of DV
, unless otherwise noted.
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
μs max
ns min
ns max
ns min
Description
SCLK cycle time
SCLK high time
SCLK low time
SYNC falling edge to SCLK falling edge setup time
16
Minimum SYNC high time (write mode)
Data setup time
Data hold time
CLEAR pulse low/high activation time
Minimum SYNC high time (read mode)
SCLK rising edge to SDO valid (SDO C
RESET pulse low time
th
SCLK falling edge to SYNC rising edge (on 24
CC
) and timed from a voltage level of 1.2 V.
Rev. A | Page 7 of 32
L
= 15 pF)
LOAD
= 2 kΩ, C
th
SCLK falling edge if using PEC)
L
= 200 pF, IOUT: R
AD5748
LOAD
=