HUF75939P3 Fairchild Semiconductor, HUF75939P3 Datasheet - Page 8

• Manufacturer Part Number: HUF75939P3
• Description: MOSFET N-CH 200V 22A TO-220AB
• Manufacturer: Fairchild Semiconductor
• Series: UltraFET™r

Specifications of HUF75939P3

• Fet Type: MOSFET N-Channel, Metal Oxide
• Fet Feature: Logic Level Gate
• Rds On (max) @ Id, Vgs: 125 mOhm @ 22A, 10V
• Drain To Source Voltage (vdss): 200V
• Current - Continuous Drain (id) @ 25° C: 22A
• Vgs(th) (max) @ Id: 4V @ 250µA
• Gate Charge (qg) @ Vgs: 152nC @ 20V
• Input Capacitance (ciss) @ Vds: 2200pF @ 25V
• Power - Max: 180W
• Mounting Type: Through Hole
• Package / Case: TO-220-3 (Straight Leads)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SABER Electrical Model
REV 10 October 2000
template huf75939 n2,n1,n3
electrical n2,n1,n3
{
var i iscl
dp..model dbodymod = (isl = 1.2e-12, rs=5.5e-3, trs1=1e-5, trs2=8e-6, cjo = 12.5e-10, m=0.42, tt = 1e-7, xti = 5.5)
dp..model dbreakmod = (rs=2.5, trs1=1e-3, trs2=-8.9e-6)
dp..model dplcapmod = (cjo = 2.5e-9, isl =10e-30, nl=10, m = 0.9)
m..model mmedmod = (type=_n, vto = 3.14, kp = 5, is = 1e-30, tox = 1)
m..model mstrongmod = (type=_n, vto = 3.68, kp = 100, is = 1e-30, tox = 1)
m..model mweakmod = (type=_n, vto = 2.76, kp = 0.05, is = 1e-30, tox = 1, rs = 0.1)
sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -8.5, voff = -1)
sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = -1, voff = -8.5)
sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -0.1, voff = 0.2)
sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0.2, voff = -0.1)
c.ca n12 n8 = 3.6e-9
c.cb n15 n14 = 3.5e-9
c.cin n6 n8 = 2e-9
dp.dbody n7 n5 = model=dbodymod
dp.dbreak n5 n11 = model=dbreakmod
dp.dplcap n10 n5 = model=dplcapmod
i.it n8 n17 = 1
l.ldrain n2 n5 = 1e-9
l.lgate n1 n9 = 5.78e-9
l.lsource n3 n7 = 3.92e-9
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
res.rbreak n17 n18 = 1, tc1 = 1.52e-3, tc2 = -2e-7
res.rdrain n50 n16 = 83.5e-3, tc1 = 9.8e-3, tc2 = 2.6e-5
res.rgate n9 n20 = 7.6e-1
res.rldrain n2 n5 = 10
res.rlgate n1 n9 = 57.8
res.rlsource n3 n7 = 39.2
res.rslc1 n5 n51 = 1e-6, tc1 = 3e-3, tc2 = 1e-6
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 10e-3, tc1 = 1e-3, tc2 = 1e-6
res.rvtemp n18 n19 = 1, tc1 = -2.8e-3, tc2 = 1.7e-6
res.rvthres n22 n8 = 1, tc1 = -2.3e-3, tc2 = -1.3e-5
spe.ebreak n11 n7 n17 n18 = 225
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/38))** 2.5))
}
}
©2001 Fairchild Semiconductor Corporation
GATE
1
RLGATE
LGATE
9
RGATE
CA
12
20
EVTEMP
+
S1A
S1B
ESG
18
22
EGS
13
8
+
-
-
13
6
8
10
+
+
-
-
14
13
6
6
8
RSLC2
S2A
S2B
DPLCAP
EVTHRES
+
EDS
19
8
15
CB
CIN
-
+
-
5
8
5
MSTRO
14
51
21
RSLC1
50
RDRAIN
ISCL
16
8
MMED
8
DBREAK
IT
RSOURCE
MWEAK
17
EBREAK
RVTHRES
RBREAK
11
+
-
17
18
HUF75939P3, HUF75939S3ST Rev. B
7
+
-
18
22
RVTEMP
19
RLSOURCE
LSOURCE
VBAT
RLDRAIN
LDRAIN
DBODY
SOURCE
DRAIN
2
3