FQA24N50F Fairchild Semiconductor, FQA24N50F Datasheet - Page 5
![MOSFET N-CH 500V 24A TO-3P](/photos/26/98/269851/to3p_sml.jpg)
FQA24N50F
Manufacturer Part Number
FQA24N50F
Description
MOSFET N-CH 500V 24A TO-3P
Manufacturer
Fairchild Semiconductor
Series
FRFET™r
Datasheet
1.FQA24N50F.pdf
(8 pages)
Specifications of FQA24N50F
Fet Type
MOSFET N-Channel, Metal Oxide
Fet Feature
Standard
Rds On (max) @ Id, Vgs
200 mOhm @ 12A, 10V
Drain To Source Voltage (vdss)
500V
Current - Continuous Drain (id) @ 25° C
24A
Vgs(th) (max) @ Id
5V @ 250µA
Gate Charge (qg) @ Vgs
120nC @ 10V
Input Capacitance (ciss) @ Vds
4500pF @ 25V
Power - Max
290W
Mounting Type
Through Hole
Package / Case
TO-3PN-3
Configuration
Single
Transistor Polarity
N-Channel
Resistance Drain-source Rds (on)
0.2 Ohms
Forward Transconductance Gfs (max / Min)
22 S
Drain-source Breakdown Voltage
500 V
Gate-source Breakdown Voltage
+/- 30 V
Continuous Drain Current
24 A
Power Dissipation
290 W
Maximum Operating Temperature
+ 150 C
Mounting Style
Through Hole
Minimum Operating Temperature
- 55 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
FQA24N50F
Manufacturer:
FAIRCHILD
Quantity:
12 500
Company:
Part Number:
FQA24N50F
Manufacturer:
FSC
Quantity:
86 755
Part Number:
FQA24N50F
Manufacturer:
FAIRCHILD/仙童
Quantity:
20 000
©2001 Fairchild Semiconductor Corporation
10V
10V
10V
10V
12V
12V
t
t
p
p
3mA
3mA
200nF
200nF
R
R
R
R
G
G
G
G
50KΩ
50KΩ
V
V
V
V
GS
GS
GS
GS
Unclamped Inductive Switching Test Circuit & Waveforms
V
V
300nF
300nF
I
I
I
V
V
DS
DS
D
D
D
DS
DS
Resistive Switching Test Circuit & Waveforms
Gate Charge Test Circuit & Waveform
DUT
DUT
DUT
DUT
Same Type
Same Type
DUT
DUT
L
L L
as DUT
as DUT
R
R
L
L
V
V
DD
DD
V
V
DD
DD
V
V
DS
DS
BV
BV
V
V
V
V
10V
10V
DSS
DSS
V
V
I
I
V
V
DD
DD
GS
GS
AS
AS
DS
DS
GS
GS
E
E
E
10%
10%
AS
AS
AS
Q
Q
90%
90%
=
=
=
gs
gs
t
t
d(on)
d(on)
----
----
----
----
1
1
1
1
2
2
2
2
t
t
on
on
L I
L I
L I
t
t
r
r
I
I
AS
AS
AS
D
D
Q
Q
(t)
(t)
t
t
2
2
2
Q
Q
p
p
g
g
gd
gd
Charge
Charge
--------------------
--------------------
BV
BV
BV
BV
DSS
DSS
DSS
DSS
t
t
- V
- V
d(off)
d(off)
t
t
DD
DD
off
off
Time
Time
Rev. A2, September 2001
t
t
f
f
V
V
DS
DS
(t)
(t)