FDS6679AZ Fairchild Semiconductor, FDS6679AZ Datasheet - Page 2

• Manufacturer Part Number: FDS6679AZ
• Description: MOSFET P-CH 30V 13A 8-SOIC
• Manufacturer: Fairchild Semiconductor
• Series: PowerTrench®r

Specifications of FDS6679AZ

• Fet Type: MOSFET P-Channel, Metal Oxide
• Fet Feature: Logic Level Gate
• Rds On (max) @ Id, Vgs: 9.3 mOhm @ 13A, 10V
• Drain To Source Voltage (vdss): 30V
• Current - Continuous Drain (id) @ 25° C: 13A
• Vgs(th) (max) @ Id: 3V @ 250µA
• Gate Charge (qg) @ Vgs: 96nC @ 10V
• Input Capacitance (ciss) @ Vds: 3845pF @ 15V
• Power - Max: 1W
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Configuration: Single Quad Drain Triple Source
• Transistor Polarity: P-Channel
• Resistance Drain-source Rds (on): 0.0093 Ohm @ 10 V
• Drain-source Breakdown Voltage: 30 V
• Gate-source Breakdown Voltage: +/- 25 V
• Continuous Drain Current: 13 A
• Power Dissipation: 2500 mW
• Maximum Operating Temperature: + 150 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 55 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: FDS6679AZTR

©2009 Fairchild Semiconductor Corporation
FDS6679AZ Rev. B2
Electrical Characteristics
Off Characteristics
On Characteristics
Dynamic Characteristics
Switching Characteristics
Drain-Source Diode Characteristic
B
∆B
I
I
V
r
g
C
C
C
t
t
t
t
Q
Q
Q
Q
V
t
Q
Notes:
1: R
2: Pulse Test:Pulse Width <300µs, Duty Cycle <2.0%
3: The diode connected between the gate and source serves only as protection against ESD. No gate overvoltage rating is implied.
∆V
d(on)
d(off)
f
DSS
GSS
DS(on)
r
rr
FS
VDSS
GS(th)
SD
iss
oss
rss
∆T
∆T
g
g
gs
gd
rr
Symbol
VDSS
drain pins. R
GS(th)
θJA
J
J
Scale 1 : 1 on letter size paper
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the
θJC
Drain to Source Breakdown Voltage
Breakdown Voltage Temperature
Coefficient
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
Gate to Source Threshold Voltage
Gate to Source Threshold Voltage
Temperature Coefficient
Drain to Source On Resistance
Forward Transconductance
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Total Gate Charge
Total Gate Charge
Gate to Source Gate Charge
Gate to Drain Charge
Source to Drain Diode Forward Voltage V
Reverse Recovery Time
Reverse Recovery Charge
is guaranteed by design while R
(Note 2)
a) 50°C/W when
Parameter
mounted on a 1 in
pad of 2 oz copper
(Note 2)
θCA
T
J
is determined by the user’s board design.
= 25°C unless otherwise noted
2
I
I
25°C
V
V
V
I
25°C
V
V
V
T
V
V
f = 1MHz
V
V
V
I
V
I
I
I
D
D
D
D
D
F
F
J
DS
GS
GS
GS
GS
GS
DS
DS
DD
GS
DS
DS
GS
= -13A, di/dt = 100A/µs
= -13A, di/dt = 100A/µs
= -250µA, V
= -250µA, referenced to
= -250µA, referenced to
= -13A
= -13A
= 125°C
= -24V, V
= -5V, I
= -15V, V
= -15V, V
= -15V, V
= ±25V, V
= V
= -10V, I
= -4.5V, I
= -10V, I
= -15V, I
= -10V, R
= 0V, I
2
Test Conditions
DS
, I
b)105°C/W when
mounted on a .04 in
pad of 2 oz copper
S
D
D
D
D
D
= -2.1A
D
= -13A
GS
GS
GS
GS
GS
GS
DS
= -13A
= -13A,
= -1A
= -250µA
= -11A
=0V
=0V
= -10V,
= -5V,
= 0V,
= 6Ω
= 0V
2
Min
-30
-1
2890
11.8
10.7
Typ
-1.9
500
495
-0.7
210
-20
6.5
7.7
55
13
15
92
68
38
10
17
minimun pad
c) 125°C/W when
mounted on a
www.fairchildsemi.com
3845
Max
14.8
13.4
±10
665
745
336
148
-1.2
9.3
-31
24
27
96
54
40
-1
-3
mV/°C
mV/°C
Units
mΩ
µA
µA
pF
pF
pF
nC
nC
nC
nC
nC
ns
ns
ns
ns
ns
V
V
S
V