FDD4685 Fairchild Semiconductor, FDD4685 Datasheet - Page 2

• Manufacturer Part Number: FDD4685
• Description: MOSFET P-CH 40V 8.4A DPAK
• Manufacturer: Fairchild Semiconductor
• Series: PowerTrench®r

Specifications of FDD4685

• Fet Type: MOSFET P-Channel, Metal Oxide
• Fet Feature: Logic Level Gate
• Rds On (max) @ Id, Vgs: 27 mOhm @ 8.4A, 10V
• Drain To Source Voltage (vdss): 40V
• Current - Continuous Drain (id) @ 25° C: 8.4A
• Vgs(th) (max) @ Id: 3V @ 250µA
• Gate Charge (qg) @ Vgs: 27nC @ 5V
• Input Capacitance (ciss) @ Vds: 2380pF @ 20V
• Power - Max: 3W
• Mounting Type: Surface Mount
• Package / Case: DPak, TO-252 (2 leads+tab), SC-63
• Configuration: Single
• Transistor Polarity: P-Channel
• Resistance Drain-source Rds (on): 0.027 Ohm @ 10 V
• Drain-source Breakdown Voltage: 40 V
• Gate-source Breakdown Voltage: +/- 20 V
• Continuous Drain Current: 8.4 A
• Power Dissipation: 69000 mW
• Maximum Operating Temperature: + 150 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 55 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: FDD4685TR

FDD4685 Rev.B
Electrical Characteristics
Off Characteristics
On Characteristics
Dynamic Characteristics
Switching Characteristics
Drain-Source Diode Characteristics
Notes:
1: R
2: Pulse Test: Pulse Width < 300µs, Duty cycle < 2.0%.
3: Starting T
BV
∆BV
I
I
V
r
g
C
C
C
R
t
t
t
t
Q
Q
Q
V
t
Q
∆V
DSS
GSS
d(on)
r
d(off)
f
rr
DS(on)
FS
GS(th)
SD
iss
oss
rss
g
∆T
∆T
g(TOT)
gs
gd
rr
R
Symbol
a. 40°C/W when mounted on a 1 in
b. 96°C/W when mounted on a minimum pad.
DSS
θJA
θJC
GS(th)
DSS
J
J
is the sum of the junction-to-case and case-to- ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins.
is guaranteed by design while R
J
= 25°C, L = 3mH, I
Drain to Source Breakdown Voltage
Breakdown Voltage Temperature
Coefficient
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
Gate to Source Threshold Voltage
Gate to Source Threshold Voltage
Temperature Coefficient
Static Drain to Source On Resistance
Forward Transconductance
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Gate Resistance
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Total Gate Charge
Gate to Source Gate Charge
Gate to Drain “Miller” Charge
Source to Drain Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
AS
(Note 2)
= 9A, V
2
Parameter
θJA
pad of 2 oz copper
DD
is determined by the user’s board design.
= 40V, V
T
GS
J
= 10V.
= 25°C unless otherwise noted
V
V
V
V
V
f = 1MHz
f = 1MHz
V
I
V
V
V
V
V
I
I
I
V
V
D
F
D
D
DD
GS
DD
GS
GS
GS
GS
GS
DS
DS
GS
DS
GS
= –8.4A, di/dt = 100A/µs
= –250µA, referenced to 25°C
= –250µA, V
= –250µA, referenced to 25°C
= –5V
= –20V, V
= –20V, I
= –10V, R
=–20V, I
= –10V, I
= –5V, I
= 0V, I
= –32V, V
= V
= –10V, I
= –4.5V, I
= ±20V, V
2
DS
Test Conditions
, I
S
D
D
= –8.4A
D
D
D
D
D
GS
GEN
= –8.4A
GS
= –8.4A
= –250µA
GS
= –8.4A, T
= –8.4A
= –8.4A
GS
= –7A
= 0V,
= 0V
= 0V
= 6Ω
= 0V
(Note 2)
J
=125°C
Min
–40
–1
–0.85
1790
–1.6
260
140
5.6
6.1
Typ
4.9
30
31
–33
15
34
14
19
23
30
33
23
4
8
2380
–1.2
±100
Max
345
205
16
27
55
26
27
45
47
–3
27
35
42
–1
www.fairchildsemi.com
mV/°C
mV/°C
Units
mΩ
nC
pF
pF
pF
nC
nC
nC
µA
nA
ns
ns
ns
ns
ns
Ω
V
V
S
V