FDW2503NZ Fairchild Semiconductor, FDW2503NZ Datasheet - Page 2

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FDW2503NZ

Manufacturer Part Number
FDW2503NZ
Description
MOSFET N-CH DUAL 20V 5.5A 8-TSSO
Manufacturer
Fairchild Semiconductor
Series
PowerTrench®r
Datasheet

Specifications of FDW2503NZ

Fet Type
2 N-Channel (Dual)
Fet Feature
Logic Level Gate
Rds On (max) @ Id, Vgs
20 mOhm @ 5.5A, 4.5V
Drain To Source Voltage (vdss)
20V
Current - Continuous Drain (id) @ 25° C
5.5A
Vgs(th) (max) @ Id
1.5V @ 250µA
Gate Charge (qg) @ Vgs
17nC @ 4.5V
Input Capacitance (ciss) @ Vds
1286pF @ 10V
Power - Max
600mW
Mounting Type
Surface Mount
Package / Case
8-TSSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
FDW2503NZ
Manufacturer:
FAIRCHILD/仙童
Quantity:
20 000
Notes:
1. R
2. Pulse Test: Pulse Width < 300 s, Duty Cycle < 2.0%
3. The diode connected between the gate and source serves only as protection against ESD. No gate overvoltage rating is implied.
Electrical Characteristics
Symbol
Off Characteristics
BV
I
I
I
On Characteristics
V
R
I
g
Dynamic Characteristics
C
C
C
Switching Characteristics
t
t
t
t
Q
Q
Q
Drain–Source Diode Characteristics and Maximum Ratings
I
V
DSS
GSSF
GSSR
D(on)
S
the drain pins. R
a)
b)
d(on)
r
d(off)
f
FS
BV
V
DS(on)
iss
oss
rss
GS(th)
g
gs
gd
SD
JA
DSS
GS(th)
T
T
R
R
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of
DSS
J
J
JA
JA
is 100 C/W (steady state) when mounted on a 1 inch² copper pad on FR-4.
is 125 C/W (steady state) when mounted on a minimum copper pad on FR-4.
Drain–Source Breakdown Voltage
Breakdown Voltage Temperature
Coefficient
Zero Gate Voltage Drain Current
Gate–Body Leakage, Forward
Gate–Body Leakage, Reverse
Gate Threshold Voltage
Gate Threshold Voltage
Temperature Coefficient
Static Drain–Source
On–Resistance
On–State Drain Current
Forward Transconductance
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Turn–On Delay Time
Turn–On Rise Time
Turn–Off Delay Time
Turn–Off Fall Time
Total Gate Charge
Gate–Source Charge
Gate–Drain Charge
Maximum Continuous Drain–Source Diode Forward Current
Drain–Source Diode Forward
Voltage
JC
is guaranteed by design while R
Parameter
(Note 2)
(Note 2)
CA
is determined by the user's board design.
T
A
V
I
V
V
V
V
I
V
V
V
V
V
V
f = 1.0 MHz
V
V
V
V
V
D
D
= 25°C unless otherwise noted
GS
DS
GS
GS
DS
GS
GS
GS
GS
DS
DS
DD
GS
DS
GS
GS
= 250 A, Referenced to 25 C
= 250 A, Referenced to 25 C
= 4.5 V, I
= 0 V, I
= 16 V,
= 12 V,
= –12 V, V
= V
= 4.5 V,
= 2.5 V,
= 4.5 V,
= 5 V,
= 10 V,
= 10 V,
= 4.5 V,
= 10 V,
= 4.5 V
= 0 V, I
Test Conditions
GS
, I
D
D
= 250 A
D
S
= 250 A
= 5.5 A, T
= 1.0 A
V
V
I
I
V
I
GS
DS
DS
D
D
D
V
I
I
R
D
D
= 5.5 A
= 5 A
GS
GEN
= 5.5 A,
DS
= 5.5 A
= 1 A,
= 0 V
= 0 V
= 0 V
= 0 V,
= 5 V
= 6
J
(Note 2)
=125 C
Min
0.6
20
30
1286
Typ
305
161
1.0
2.6
0.7
14
–3
14
19
19
30
10
14
25
12
8
3
Max Units
–10
1.5
1.0
1.2
10
20
26
29
20
25
40
16
17
FDW2503NZ Rev C1(W)
1
mV/ C
mV/ C
m
nC
nC
nC
pF
pF
pF
ns
ns
ns
ns
V
V
A
S
A
V
A
A
A

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