AD9866BCP Analog Devices Inc, AD9866BCP Datasheet - Page 42

• Manufacturer Part Number: AD9866BCP
• Description: IC FRONT-END MIXED-SGNL 64-LFCSP
• Manufacturer: Analog Devices Inc

Specifications of AD9866BCP

• Rohs Status: RoHS non-compliant
• Rf Type: HPNA, VDSL
• Features: 12-bit ADC(s), 12-bit DAC(s)
• Package / Case: 64-VFQFN, CSP Exposed Pad
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3/3.135V
• Operating Supply Voltage (max): 3.6/3.465V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Package Type: LFCSP
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / RoHS Status: Not Compliant

AD9866
A sine wave input is a standard and convenient method of
analyzing the performance of a system. However, the amount of
power reduction that is possible is application dependent, based
on the nature of the input waveform (such as frequency content,
peak-to-rms ratio), the minimum ADC sample, and the mini-
mum acceptable level of performance. Thus, it is advisable that
power-sensitive applications optimize the power bias setting of
the Rx path using an input waveform that is representative of
the application.
POWER DISSIPATION
The power dissipation of the AD9866 can become quite high in
full-duplex applications in which the Tx and Rx paths are si-
multaneously operating with nominal power bias settings. In
fact, some applications that use the IAMP may need to either
reduce its peak power capabilities or reduce the power con-
sumption of the Rx path, so that the device’s maximum
allowable power consumption, P
P
does not exceed 125
specification is based on the 64-pin LFSCP having a thermal
resistance, θ
MAX
Figure 84. SNR and THD Performance vs. f
is specified at 1.66 W to ensure that the die temperature
65
64
63
62
61
60
59
58
57
56
55
Figure 83. AVDD Current vs. ADC Bias Setting and Sample Rate
220
210
200
190
180
170
160
150
140
130
120
20
20
JA
, of 24
RxPGA = 0 dB, f
30
SNR-000
SNR-001
SNR-010
SNR-011
SNR-100
SNR-101
30
o
o
C/W with its heat slug soldered. (The θ
C at an ambient temperature of 85
40
SAMPLE RATE (MSPS)
THD-000
THD-001
THD-010
THD-011
THD-100
THD-101
40
SAMPLE RATE (MSPS)
IN
= 10 MHz, AIN = −1 dBFS
101 OR 111
100
50
MAX
50
, is not exceeded.
001
011
010
000
ADC
60
and ADC Bias Setting with
60
101
70
70
80
o
C. This
–54
–56
–58
–60
–62
–64
–66
–68
–70
–72
–74
80
JA
Rev. A | Page 42 of 48
is
30.8
application’s maximum ambient temperature, T
85
mined by the following equation:
Assuming the IAMP’s common-mode bias voltage is operating
off the same analog supply as the AD9866, the following equa-
tion can be used to calculate the maximum total current
consumption, I
With an ambient temperature of up to 85°C, I
If the IAMP is operating off a different supply or in the voltage
mode configuration, first calculate the power dissipated in the
IAMP, P
late I
Figure 78, Figure 79, Figure 81, and Figure 83 can be used to
calculate the current consumption of the Rx and Tx paths for a
given setting.
MODE SELECT UPON POWER-UP AND RESET
The AD9866 power-up state is determined by the logic levels
appearing at the MODE and CONFIG pins. The MODE pin is
used to select a half- or full-duplex interface by pin strapping it
low or high, respectively. The CONFIG pin is used in conjunc-
tion with the MODE pin to determine the default settings for
the SPI registers as outlined in Table 10.
The intent of these particular default settings is to allow some
applications to avoid using the SPI (disabled by pin-strapping
SEN high), thereby reducing implementation costs. For
example, setting MODE low and CONFIG high configures the
AD9866 to be backward-compatible with the AD9975, while
setting MODE high and CONFIG low makes it backward-
compatible with the AD9875. Other applications must use the
SPI to configure the device.
A hardware ( RESET pin) or software (Bit 5 of Register 0x00)
reset can be used to place the AD9866 into a known state of
operation as determined by the state of the MODE and CONFIG
pins. A dc offset calibration and filter tuning routine is also
initiated upon a hardware reset, but not with a software reset.
Neither reset method flushes the digital interpolation filters in
the Tx path. Refer to the Half-Duplex Mode and Full-Duplex
Mode sections for information on flushing the digital filters.
A hardware reset can be triggered by pulsing the RESET pin low
for a minimum of 50 ns. The SPI registers are instantly reset to
their default settings upon RESET going low, while the dc offset
calibration and filter tuning routine is initiated upon RESET
returning high. To ensure sufficient power-on time of the
o
C, the maximum allowable power dissipation can be deter-
o
P
I
C/W, if the heat slug remains unsoldered.) If a particular
MAX
MAX
MAX
, using Equation 14.
IAMP
= (P
= 1.66 + (85 − T
, using Equation 2 or Equation 5, and then recalcu-
MAX
MAX
− P
, of the IC:
IAMP
)/3.47
A
)/24
MAX
A
, falls below
is 478 mA.
(13)
(14)