AD9866BCP Analog Devices Inc, AD9866BCP Datasheet
AD9866BCP
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AD9866BCP Summary of contents
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FEATURES Low cost 3.3 V CMOS MxFE TM for broadband modems 12-bit D/A converter 2×/4× interpolation filter 200 MSPS DAC update rate Integrated 23 dBm line driver with 19.5 dB gain control 12-bit, 80 MSPS A/D converter − ...
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AD9866 TABLE OF CONTENTS Specifications..................................................................................... 3 Tx Path Specifications.................................................................. 3 Rx Path Specifications.................................................................. 4 Power Supply Specifications ....................................................... 5 Digital Specifications ................................................................... 6 Serial Port Timing Specifications............................................... 7 Half-Duplex Data Interface (ADIO Port) Timing Specifications ................................................................................ 7 Full-Duplex Data Interface ...
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SPECIFICATIONS Tx PATH SPECIFICATIONS AVDD = 3.3 V ± 5%, DVDD = CLKVDD = DRVDD = 3.3 V ± 10%; f noted. Table 1. Parameter TxDAC DC CHARACTERISTICS Resolution Update Rate Full-Scale Output Current (IOUTP_FS) 1 Gain Error Offset Error ...
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AD9866 Parameter −3 dB Bandwidth Stop Band Rejection (0.289 f to 0.711 f OSCIN PLL CLK MULTIPLIER OSCIN Frequency Range Internal VCO Frequency Range Duty Cycle OSCIN Impedance 5 CLKOUT1 Jitter 6 CLKOUT2 Jitter 7 CLKOUT1 and CLKOUT2 Duty Cycle ...
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Parameter Rx PATH COMPOSITE AC PERFORMANCE @ f RxPGA Gain = 48 dB (Full-Scale = 8.0 mV p-p) Signal-to-Noise (SNR) Total Harmonic Distortion (THD) RxPGA Gain = 24 dB (Full-Scale = 126 mV p-p) Signal-to-Noise (SNR) Total Harmonic Distortion (THD) ...
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AD9866 Parameter Rx Mode AVDD CLKVDD DVDD DRVDD POWER CONSUMPTION OF FUNCTIONAL BLOCKS RxPGA and LPF ADC TxDAC IAMP (Programmable) Reference CLK PLL and Synthesizer MAXIMUM ALLOWABLE POWER DISSIPATION STANDBY POWER CONSUMPTION IS_TOTAL (Total ...
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SERIAL PORT TIMING SPECIFICATIONS AVDD = 3.3 V ± 5%, DVDD = CLKVDD = DRVDD = 3.3 V ± 10%, unless otherwise noted. Table 5. Parameter WRITE OPERATION (See Figure 46) SCLK Clock Rate (f ) SCLK SCLK Clock High ...
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AD9866 FULL-DUPLEX DATA INTERFACE (Tx AND Rx PORT) TIMING SPECIFICATIONS AVDD = 3.3 V ± 5%, DVDD = CLKVDD = DRVDD = 3.3 V ± 10%, unless otherwise noted. Table 7. Parameter Tx PATH INTERFACE (See Figure 53) Input Nibble ...
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ABSOLUTE MAXIMUM RATINGS Table 8. Parameter ELECTRICAL AVDD, CLKVDD Voltage DVDD, DRVDD Voltage RX+, RX−, REFT, REFB IOUTP+, IOUTP− IOUTN+, IOUTN−, IOUTG+, IOUTG− OSCIN, XTAL REFIO, REFADJ Digital Input and Output Voltage Digital Output Current ENVIRONMENTAL Operating Temperature Range (Ambient) ...
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AD9866 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS ADIO11/Tx[5] ADIO10/Tx[4] ADIO9/Tx[3] ADIO8/Tx[2] ADIO7/Tx[1] ADIO6/Tx[0] ADIO5/Rx[5] ADIO4/Rx[4] ADIO3/Rx[3] ADIO2/Rx[2] ADIO1/Rx[1] ADIO0/Rx[0] RXEN/RXSYNC TXEN/TXSYNC TXCLK/TXQUIET RXCLK Table 9. Pin Function Descriptions Pin No. Mnemonic 1 ADIO11 Tx[ ADIO10 to 7 Tx[4 ...
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Pin No. Mnemonic 16 RXCLK 17, 64 DRVDD 18, 63 DRVSS 19 CLKOUT1 20 SDIO 21 SDO 22 SCLK 23 SEN 24 GAIN PGA[ PGA RESET 31, 34, 36, 39, 44, 47, 48 AVSS ...
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AD9866 TYPICAL PERFORMANCE CHARACTERISTICS Rx PATH TYPICAL PERFORMANCE CHARACTERISTICS AVDD = CLKVDD = DVDD = DRVDD = 3 RIN = 50 Ω, half- or full-duplex interface, default power bias settings. 10 FUND = –1dBFS SINAD = 61.9dBFS 0 ...
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Rx PATH TYPICAL PERFORMANCE CHARACTERISTICS AVDD = CLKVDD = DVDD = DRVDD = 3 RIN = 50 Ω, half- or full-duplex interface, default power bias settings. 10 FUND = –1dBFS SINAD = 62.4dBFS 0 ENOB = 10.1BITS SNR ...
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AD9866 65.0 64.5 64.0 63.5 63.0 62.5 62.0 61.5 61.0 60.5 60 INPUT FREQUENCY (MHz) Figure 15. SNR and THD vs. Input Frequency and Supply ( LPF MHz; RxPGA = 0 dB) −3 ...
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Rx PATH TYPICAL PERFORMANCE CHARACTERISTICS AVDD = CLKVDD = DVDD = DRVDD = 3 RIN = 50 Ω, half- or full-duplex interface, default power bias settings. 2048 1792 1536 1280 1024 768 512 256 0 80 160 240 ...
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AD9866 TxDAC PATH TYPICAL PERFORMANCE CHARACTERISTICS AVDD = CLKVDD = DVDD = DRVDD = 3.3 V, fOSCIN = 50 MSPS and 80 MSPS, RSET = 1.96 kΩ, 2:1 transformer coupled output (see Figure 63) into 50 Ω load half-or full-duplex ...
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FREQUENCY (MHz) Figure 33. Spectral Plot of 84-Carrier OFDM Test Vector MSPS, 4× Interpolation) DATA –20 PAR = 11.4 RMS = –1.4dBm –30 –40 ...
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AD9866 IAMP PATH TYPICAL PERFORMANCE CHARACTERISTICS AVDD = CLKVDD = DVDD = DRVDD = 3 Figure 65) into 50 Ω load, half- or full-duplex interface, default power bias settings –5 –10 –15 –20 ...
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SERIAL PORT Table 10. SPI Register Mapping Bit Address Break- 1 (Hex) down Description SPI PORT CONFIGURATION AND SOFTWARE RESET 0x00 (7) 4-Wire SPI (6) LSB First (5) S/W Reset POWER CONTROL REGISTERS (via PWR_DWN pin) 0x01 (7) Clock Syn. ...
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AD9866 Bit Address Break- 1 (Hex) down Description 0x08 (7:0) Rx Filter Tuning Cutoff Frequency Tx/Rx PATH GAIN CONTROL 0x09 (6) Use SPI Rx Gain (5:0) Rx Gain Code 0x0A (6) Use SPI Tx Gain (5:0) Tx Gain Code Tx ...
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Bit Address Break- 1 (Hex) down Description 0x13 (7:5) CPGA Bias Adjust (4:3) SPGA Bias Adjust (2:0) ADC Bias Adjust 1 Bits that are undefined should always be assigned a 0. REGISTER MAP DESCRIPTION The AD9866 contains a set of ...
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AD9866 INSTRUCTION CYCLE DATA TRANSFER CYCLE SEN SCLK SDATA R INSTRUCTION CYCLE DATA TRANSFER CYCLE SEN SCLK SDATA R ...
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DIGITAL INTERFACE The digital interface port is configurable for half-duplex or full- duplex operation by pin-strapping the MODE pin low or high, respectively. In half-duplex mode, the digital interface port becomes a 10-bit bidirectional bus called the ADIO port. In ...
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AD9866 DIGITAL ASIC ADIO [11:0] Tx/Rx Data[11:0] RXEN RXEN TXEN TXEN DAC_CLK TXCLK ADC_CLK RXCLK CLKOUT OSCIN Figure 51. Example of a Half-Duplex Digital Interface with AD9866 Serving as the Slave Figure 52 shows a half-duplex interface with the AD9866 ...
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RXCLK t DV RXSYNC Rx[5:0] Rx0LSB Rx1MSB Rx1LSB Rx2MSB Figure 54. Full-Duplex Rx Port Timing To add flexibility to the full-duplex digital interface port, several programming options are available in the SPI registers. These options are listed in Table ...
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AD9866 –6 – 6-BIT DIGITAL WORD-DECIMAL EQUIVALENT Figure 56. Digital Gain Mapping of RxPGA Table 15. SPI Registers RxPGA Control Address (Hex) Bit Description ...
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TXPGA CONTROL The AD9866 also contains a digital PGA in the Tx path distributed between the TxDAC and IAMP. The TxPGA is used to control the peak current from the TxDAC and IAMP over a 7.5 dB and 19.5 dB ...
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AD9866 TRANSMIT PATH The AD9866 (or AD9865) transmit path consists of a selectable digital 2×/4× interpolation filter, a 12-bit (or 10-bit) TxDAC, and a current-output amplifier (IAMP), as shown in Figure 59. Note that the additional two bits of resolution ...
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Applications demanding the highest spectral performance and/or lowest power consumption can use the TxDAC output directly. The TxDAC is capable of delivering a peak signal power- dBm while maintaining respectable linearity performance, as shown in Figure 27 through ...
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AD9866 Table 19. SPI Registers for TxDAC and IAMP Address (Hex) Bit Description 0x0E (0) TxDAC output 0x10 (7) Enable current mirror gain settings (6:4) Secondary path first stage gain with ∆ (3) Not ...
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The 1 transformer should be specified to handle the dc standing current drawn by the IAMP. Also, because I BIAS signal independent, a series resistor (not shown) can be inserted between ...
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AD9866 transistors remain in the active region during peak load currents. The gain of the secondary path, G, and the TxDAC’s standing current, I, can be set using the following equation: IOUT + × ...
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RECEIVE PATH The receive path block diagram for the AD9866 (or AD9865) is shown in Figure 68. The receive signal path consists of a 3-stage RxPGA, a 3-pole programmable LPF, and a 12-bit (or 10-bit) ADC. Note that the additional ...
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AD9866 LOW-PASS FILTER The low-pass filter (LPF) provides a third order response with a cutoff frequency that is typically programmable over a 15 MHz to 35 MHz span. Figure 68 shows that the first real pole is im- plemented within ...
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MSPS MEASURED 25 80 MSPS CALCULATED MSPS MEASURED 17 50 MSPS CALCULATED 112 128 144 TARGET-DECIMAL EQUIVALENT Figure 73. Measured and Calculated f for f ...
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AD9866 REFT TO C1 ADCs 0.1µF REFB 1.0V TOP VIEW Figure 75. ADC Reference and Decoupling The ADC has an internal voltage reference and reference ampli- fier as shown in Figure 75. The internal band gap ...
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CLOCK SYNTHESIZER The AD9866 generates all its internal sampling clocks, as well as two user-programmable clock outputs appearing at CLKOUT1 and CLKOUT2, from a single reference source as shown in Figure 76. The reference source can be either a fundamental ...
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AD9866 at OSCIN (or RXCLK) can be determined upon power-up. Also, this clock has near 50% duty cycle, because it is derived from the VCO result, CLKOUT1 should be selected before CLKOUT2 as the primary source for system ...
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POWER CONTROL AND DISSIPATION POWER-DOWN The AD9866 provides the ability to control the power-on state of various functional blocks. The state of the PWRDWN pin, along with the contents of Register 0x01 and Register 0x02, allow two user-defined power settings ...
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AD9866 occurs within 100 ns. The user-programmable delay for the Tx path power-down is meant to match the pipeline delay of the last Tx burst sample such that power-down of the TxDAC and IAMP does not impact its transmission. A ...
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Because the CPGA processes signals in the continuous time domain, its performance vs. bias setting remains mostly independent of the sample rate. Table 25 shows how the typical current consumption seen at AVDD (Pins 35 and 40) varies as a ...
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AD9866 220 101 OR 111 210 200 000 190 001 180 010 170 160 011 100 150 140 130 120 SAMPLE RATE (MSPS) Figure 83. AVDD Current vs. ADC Bias Setting and Sample Rate 65 64 ...
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RESET returning high should occur no less than 10 ms upon power-up digital reset signal from a microprocessor reset circuit (such as ADM1818) is not available, a simple R-C network referenced to DVDD can be ...
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AD9866 PCB DESIGN CONSIDERATIONS Although the AD9866 is a mixed-signal device, the part should be treated as an analog component. The on-chip digital cir- cuitry has been specially designed to minimize the impact of its digital switching noise on the ...
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If the signal traces cannot be kept shorter than about 1.5 inches, series termination resistors (33 Ω Ω) should be placed close to all digital signal sources ...
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AD9866 EVALUATION BOARD An evaluation board is available for the AD9865 and AD9866. The digital interface to the evaluation board can be configured for a half- or full-duplex interface. Two 40-pin and one 26-pin male right angle headers (0.100 inches) ...
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... SEATING PLANE ORDERING GUIDE Model Temperature Range AD9866BCP −40°C to +85°C AD9866BCPRL −40°C to +85°C AD9866BCPZ 1 −40°C to +85°C 1 AD9866BCPZRL −40°C to +85°C AD9866CHIPS AD9866- Pb-free part. 9.00 BSC SQ 0.60 MAX 49 48 8.75 TOP BSC SQ VIEW ...
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AD9866 NOTES © 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C04560–0–12/04(A) Rev Page ...