AD9866BCP Analog Devices Inc, AD9866BCP Datasheet - Page 3

• Manufacturer Part Number: AD9866BCP
• Description: IC FRONT-END MIXED-SGNL 64-LFCSP
• Manufacturer: Analog Devices Inc

Specifications of AD9866BCP

• Rohs Status: RoHS non-compliant
• Rf Type: HPNA, VDSL
• Features: 12-bit ADC(s), 12-bit DAC(s)
• Package / Case: 64-VFQFN, CSP Exposed Pad
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3/3.135V
• Operating Supply Voltage (max): 3.6/3.465V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Package Type: LFCSP
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / RoHS Status: Not Compliant

SPECIFICATIONS
Tx PATH SPECIFICATIONS
AVDD = 3.3 V ± 5%, DVDD = CLKVDD = DRVDD = 3.3 V ± 10%; f
noted.
Table 1.
Parameter
TxDAC DC CHARACTERISTICS
TxDAC GAIN CONTROL CHARACTERISTICS
TxDAC AC CHARACTERISTICS
IAMP DC CHARACTERISTICS
IAMPN AC CHARACTERISTICS
IAMP GAIN CONTROL CHARACTERISTICS
REFERENCE
Tx DIGITAL FILTER CHARACTERISTICS (2× INTERPOLATION)
Tx DIGITAL FILTER CHARACTERISTICS (4× Interpolation)
Resolution
Update Rate
Full-Scale Output Current (IOUTP_FS)
Gain Error
Offset Error
Voltage Compliance Range
Minimum Gain
Maximum Gain
Gain Step Size
Gain Step Accuracy
Gain Range Error
Fundamental
Signal-to-Noise and Distortion (SINAD)
Signal-to-Noise Ratio (SNR)
Total Harmonic Distortion (THD)
Spurious-Free Dynamic Range (SFDR)
IOUTN Full-Scale Current = IOUTN+ + IOUTN−
IOUTG Full-Scale Current = IOUTG+ + IOUTG−
AC Voltage Compliance Range
Fundamental
IOUTN SFDR (Third Harmonic)
Minimum Gain
Maximum Gain
Gain Step Size
Gain Step Accuracy
IOUTN Gain Range Error
Internal Reference Voltage
Reference Error
Reference Drift
Latency (Relative to 1/F
−0.2 dB Bandwidth
−3 dB Bandwidth
Stop-Band Rejection (0.289 F
Latency (Relative to 1/F
−0.2 dB Bandwidth
1
DAC
DAC
)
)
4
2
3
DAC
to 0.711 F
DAC
)
Rev. A | Page 3 of 48
OSCIN
Temp
Full
Full
Full
25°C
25°C
Full
25°C
25°C
25°C
25°C
25°C
Full
Full
Full
Full
Full
Full
Full
25°C
Full
25°C
25°C
25°C
25°C
25°C
25°C
Full
Full
Full
Full
Full
Full
Full
Full
= 50 MHz, f
Test Level
II
IV
I
V
V
V
V
IV
V
IV
IV
IV
IV
IV
IV
IV
IV
V
V
V
IV
V
I
V
V
V
V
V
V
V
V
DAC
= 200 MHz, R
Min
2
68.4
−1
66.6
68.5
2
2
1
43.3
Monotonic
Monotonic
SET
−19.5
= 2.0 kΩ, unless otherwise
−7.5
69.2
69.8
45.2
Typ
−79
0.5
0.5
0.5
12
±2
±2
81
13
0.2187
0.2405
0.1095
2
0
0
1.23
0.5
0.7
30
43
50
96
Max
200
25
+1.5
−68.7
105
150
7
3.4
AD9866
Unit
Bits
MSPS
mA
% FS
µA
V
dB
dB
dB
dB
dBm
dBc
dBc
dBc
dBc
mA
mA
V
dBm
dBc
dB
dB
dB
dB
dB
V
%
ppm/
Cycles
f
f
dB
Cycles
f
OUT
OUT
OUT
/f
/f
/f
DAC
DAC
DAC
o
C