AD9866BCP Analog Devices Inc, AD9866BCP Datasheet - Page 20

• Manufacturer Part Number: AD9866BCP
• Description: IC FRONT-END MIXED-SGNL 64-LFCSP
• Manufacturer: Analog Devices Inc

Specifications of AD9866BCP

• Rohs Status: RoHS non-compliant
• Rf Type: HPNA, VDSL
• Features: 12-bit ADC(s), 12-bit DAC(s)
• Package / Case: 64-VFQFN, CSP Exposed Pad
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3/3.135V
• Operating Supply Voltage (max): 3.6/3.465V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Package Type: LFCSP
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / RoHS Status: Not Compliant

AD9866
Address
(Hex)
0x08
Tx/Rx PATH GAIN CONTROL
0x09
0x0A
Tx AND Rx PGA CONTROL
0x0B
Tx DIGITAL FILTER AND INTERFACE
0x0C
Rx INTERFACE AND ANALOG/DIGITAL LOOPBACK
0x0D
DIGITAL OUTPUT DRIVE STRENGTH, TxDAC OUTPUT, AND REV ID
0x0E
0x0F
Tx IAMP GAIN AND BIAS CONTROL
0x10
0x11
0x12
1
Bit
Break-
down
(7:0)
(6)
(5:0)
(6)
(5:0)
(6)
(5)
(3)
(2)
(1)
(7:6)
(4)
(2)
(1)
(0)
(7)
(6)
(5)
(4)
(2)
(1)
(0)
(7)
(0)
(3:0)
(7)
(6:4)
(2:0)
(6:4)
(2:0)
(6:4)
(2:0)
Description
Rx Filter Tuning
Cutoff Frequency
Use SPI Rx Gain
Rx Gain Code
Use SPI Tx Gain
Tx Gain Code
PGA Code for Tx
PGA Code for Rx
Force GAIN strobe
Rx Gain on Tx Port
3-Bit RxPGA Port
Interpolation
Factor
Invert
TXEN/TXSYNC
LS Nibble First*
TXCLK neg. edge
Twos complement
Analog Loopback
Digital Loopback*
Rx Port 3-State
Invert
RXEN/RXSYNC
LS Nibble First*
RXCLK neg. edge
Twos complement
Low Drive
Strength
TxDAC Output
REV ID Number
Select Tx Gain
G1
N
G2
G3
Stand_Secondary
Stand_Primary
Width
8
1
6
1
6
1
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
4
1
3
3
3
3
3
3
0x80
0x00
0x7F
0
1
0
0
0
01
0
N/A
0
0
0
0
N/A
0
N/A
0
0
0
0
0x00
0x44
0x62
0x01
CONFIG = 0
MODE = 0 (Half-Duplex)
Rev. A | Page 20 of 48
Power-Up Default Value
0x61
0x00
0x7F
0
1
0
0
1**
00
0
N/A
0
0
0
0
N/A
0
N/A
0
0
0
0
0x00
0x44
0x62
0x01
CONFIG = 1
0x80
0x00
0x7F
0
1
0
1*
0
01
0
0
0
1
0
0
0
0
0
0
1
0
0
0x00
0x44
0x62
0x01
CONFIG = 0
MODE = 1 (Full-Duplex)
0x80
0x00
0x7F
0
1
0
1*
0
01
0
0
0
1
0
0
0
0
0
0
1
0
0
0x00
0x44
0x62
0x01
CONFIG = 1
Comments
Refer to Low-Pass Filter
section.
Default setting is for hardware
Rx gain code via PGA or Tx
data port.
Default setting is for Tx gain
code via SPI control.
Default setting is RxPGA
control active.
*Tx port with GAIN strobe
(AD9875/AD9876
compatible).
**3-bit RxPGA gain map
(AD9975 compatible).
Default setting is 2× interpo-
lation with LPF response.
Data format is straight binary
for half-duplex and twos
complement for full-duplex
interface.
*Full-duplex only.
Data format is straight
binary for half-duplex and
twos complement for full-
duplex interface.
Analog loopback: ADC Rx
data fed back to TxDAC.
Digital loopback: Tx input
data to Rx output port.
*Full-duplex only.
Default setting is for high
drive strength and IAMP
enabled.
Secondary path G1 = 0, 1, 2,
3, 4.
Primary path N = 0, 1, 2, 3, 4.
Secondary path stages:
G2 = 0 to 1.50 in 0.25 steps
and G3 = 0 to 6.
Standing current of primary
and secondary path.