CP3BT10G38 National Semiconductor, CP3BT10G38 Datasheet - Page 95

• Manufacturer Part Number: CP3BT10G38
• Description: IC CPU RISC W/LLC&USB 100-LQFP
• Manufacturer: National Semiconductor

Specifications of CP3BT10G38

• Applications: Connectivity Processor
• Core Processor: CR16C
• Program Memory Type: FLASH (256 kB)
• Controller Series: CP3000
• Ram Size: 10K x 8
• Interface: Bluetooth, ACCESS.bus, Audio, UART, USB, Microwire/SPI
• Number Of I /o: 37
• Voltage - Supply: 2.25 V ~ 2.75 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *CP3BT10G38

17.2.1
In asynchronous mode, the receive and transmit paths of
the audio interface operate independently, with each path
using its own bit clock and frame sync signal. Independent
clocks for receive and transmit are only used when the bit
clock and frame sync signal are supplied externally. If the bit
clock and frame sync signals are generated internally, both
paths derive their clocks from the same set of clock prescal-
ers.
17.2.2
In synchronous mode, the receive and transmit paths of the
audio interface use the same shift clock and frame sync sig-
nal. The bit shift clock and frame sync signal for both paths
are derived from the same set of clock prescalers.
17.2.3
In normal mode, each rising edge on the frame sync signal
marks the beginning of a new frame and also the beginning
of a new slot. A slot does not necessarily occupy the entire
frame. (A frame can be longer than the data word transmit-
ted after the frame sync pulse.) Typically, a codec starts
transmitting a fixed length data word (e.g. 8-bit log PCM da-
ta) with the frame sync signal, then the codec’s transmit pin
returns to the high-impedance state for the remainder of the
frame.
The Audio Receive Shift Register (ARSR) de-serializes re-
ceived on the SRD pin (serial receiver data). Only the data
sampled after the frame sync signal are treated as valid. If
the interface is interrupt-driven, valid data bits are trans-
ferred from the ARSR to the receive FIFO. If the interface is
configured for DMA, the data is transferred to the receive
DMA register 0 (ARDR0).
The serial transmit data (STD) pin is only an active output
while data is shifted out. After the defined number of data
bits have been shifted out, the STD pin returns to the high-
impedance state.
For operation in normal mode, the Slot Count Select bits
(SCS[1:0]) in the Global Configuration register (AGCR)
must be loaded with 00b (one slot per frame). In addition,
the Slot Assignment bits for receive and transmit must be
programmed to select slot 0.
If the interface is configured for DMA, the DMA slot assign-
ment bits must also be programmed to select slot 0. In this
case, the audio data is transferred to or from the receive or
transmit DMA register 0 (ARDR0/ATDR0).
Figure 30 shows the frame timing while operating in normal
mode with a long frame sync interval.
Long Frame Sync
(SFS/SRFS)
(STD/SRD)
Shift Data
Asynchronous Mode
Synchronous Mode
Normal Mode
Figure 30. Normal Mode Frame
Data
High-impedance
Frame
Data
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95
IRQ Support
If the receiver interface is configured for interrupt-driven I/O
(RXDSA0 = 0), all received data are loaded into the receive
FIFO. An IRQ is asserted as soon as the number of data
bytes or words in the receive FIFO is greater than a pro-
grammable warning limit.
If the transmitter interface is configured for interrupt-driven
I/O (TXDSA0 = 0), all data to be transmitted is read from the
transmit FIFO. An IRQ is asserted as soon as the number
data bytes or words available in the transmit FIFO is equal
or less than a programmable warning limit.
DMA Support
If the receiver interface is configured for DMA (RXDSA0 =
1), received data is transferred from the ARSR into the DMA
receive buffer 0 (ARDR0). A DMA request is asserted when
the ARDR0 register is full. If the transmitter interface is con-
figured for DMA (TXDSA0 = 1), data to be transmitted are
read from the DMA transmit buffer 0 (ATDR0). A DMA re-
quest is asserted to the DMA controller when the ATDR0
register is empty.
Figure 31 shows the data flow for IRQ and DMA mode in
normal Mode.
Network Mode
In network mode, each frame is composed of multiple slots.
Each slot may transfer 8 or 16 bits. All of the slots in a frame
must have the same length. In network mode, the sync sig-
nal marks the beginning of a new frame. Only frames with
up to four slots are supported by this audio interface.
More than two devices can communicate within a network
using the same clock and data lines. The devices connected
to the same bus use a time-multiplexed approach to share
access to the bus. Each device has certain slots assigned
to it, in which only that device is allowed to transfer data.
One master device provides the bit clock and the frame sync
signal(s). On all other (slave) devices, the bit clock and
frame sync pins are inputs.
Up to four slots can be assigned to the interface, as it sup-
ports up to four slots per frame. Any other slots within the
frame are reserved for other devices.
SRD
STD
Figure 31. IRQ/DMA Support in Normal Mode
Assignment
Assignment
DMA Slot
DMA Slot
ARSR
ATSR
ARDR 0
ATDR 0
FIFO
FIFO
RX
TX
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DMA
Request 1
IRQ
DMA
Request 0
IRQ
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