CP3BT10G38 National Semiconductor, CP3BT10G38 Datasheet - Page 36

• Manufacturer Part Number: CP3BT10G38
• Description: IC CPU RISC W/LLC&USB 100-LQFP
• Manufacturer: National Semiconductor

Specifications of CP3BT10G38

• Applications: Connectivity Processor
• Core Processor: CR16C
• Program Memory Type: FLASH (256 kB)
• Controller Series: CP3000
• Ram Size: 10K x 8
• Interface: Bluetooth, ACCESS.bus, Audio, UART, USB, Microwire/SPI
• Number Of I /o: 37
• Voltage - Supply: 2.25 V ~ 2.75 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *CP3BT10G38

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8.5.2
The FMIBDR register holds the 16-bit data for read or write
access to an information block. The FMIBDR register is
cleared after device reset. The CPU bus master has read/
write access to this register.
IBD
8.5.3
The FM0WER register controls section-level write protec-
tion for the first half of the flash program memory. The
FMS0WER registers controls section-level write protection
for the flash data memory. Each data block is divided into 16
8K-byte sections. Each bit in the FM0WER and FSM0WER
registers controls write protection for one of these sections.
The FM0WER and FSM0WER registers are cleared after
device reset, so the flash memory is write protected after re-
set. The CPU bus master has read/write access to this reg-
isters.
FM0WEn
15
15
Flash Memory Information Block Data Register
(FMIBDR/FSMIBDR)
Flash Memory 0 Write Enable Register
(FM0WER/FSM0WER)
The Information Block Data field holds the
data word for access to an information block.
For write operations the IBD field holds the
data word to be programmed into the informa-
tion block location specified by the IBA ad-
dress. During a read operation from an
information block, the IBD field receives the
data word read from the location specified by
the IBA address.
The Flash Memory 0 Write Enable n bits con-
trol write protection for a section of a flash
memory data block. The address mapping of
the register bits is shown below.
1
Bit
–
15
0
14
FM0WE
IBD
Logical Address Range
01 E000h
00 0000h
. . .
–
–
00 1FFFh
01 FFFFh
0
0
36
8.5.4
The FM1WER register controls write protection for the sec-
ond half of the program flash memory. The data block is di-
vided into 16 8K-byte sections. Each bit in the FM1WER
register controls write protection for one of these sections.
The FM1WER register is cleared after device reset, so the
flash memory is write protected after reset. The CPU bus
master has read/write access to this registers.
FM1WEn
8.5.5
The FSM0WER register controls write protection for the
flash data memory. The data block is divided into 16 512-
byte sections. Each bit in the FSM0WER register controls
write protection for one of these sections. The FSM0WER
register is cleared after device reset, so the flash memory is
write protected after reset. The CPU bus master has read/
write access to this registers.
FSM0WEn
15
15
Flash Memory 1 Write Enable Register
(FM1WER)
Flash Data Memory 0 Write Enable Register
(FSM0WER)
The Flash Memory 1 Write Enable n bits con-
trol write protection for a section of a flash
memory data block. The address mapping of
the register bits is shown below.
The Flash Data Memory 0 Write Enable n bits
control write protection for a section of a flash
memory data block. The address mapping of
the register bits is shown below.
1
1
Bit
Bit
–
15
–
15
0
0
14
14
FSM0WE
FM1WE
Logical Address Range
Logical Address Range
0E 1E00h
03 E000h
0E 0000h
02 0000h
. . .
. . .
–
–
–
–
02 1FFFh
03 FFFFh
0E 01FFh
0E 1FFFh
0
0