CP3BT10G38 National Semiconductor, CP3BT10G38 Datasheet - Page 59

• Manufacturer Part Number: CP3BT10G38
• Description: IC CPU RISC W/LLC&USB 100-LQFP
• Manufacturer: National Semiconductor

Specifications of CP3BT10G38

• Applications: Connectivity Processor
• Core Processor: CR16C
• Program Memory Type: FLASH (256 kB)
• Controller Series: CP3000
• Ram Size: 10K x 8
• Interface: Bluetooth, ACCESS.bus, Audio, UART, USB, Microwire/SPI
• Number Of I /o: 37
• Voltage - Supply: 2.25 V ~ 2.75 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *CP3BT10G38

HCCM
HCCH
12.6.2
The Management Status Register (PMMR) is a byte-wide,
read/write register that provides status signals for the vari-
ous clocks. The reset value of PMSR register bits 0 to 2 de-
pend on the status of the clock sources monitored by the
PMM. The upper 5 bits are clear after reset. The format of
the register is shown below.
OLC
7
Power Management Status Register (PMMSR)
up event is detected. This bit must be set in
Idle and Halt modes.
0
1
The Hardware Clock Control for Main Clock
bit may be used in Power Save and Idle
modes to disable the high-frequency oscillator
conditionally, depending on whether the Blue-
tooth LLC is in Sleep mode. The DMC bit must
be clear for this mechanism to operate. The
HCCM bit is automatically cleared when the
device enters Active mode.
0
1
The Hardware Clock Control for High-Fre-
quency (PLL) bit may be used in Power Save
and Idle modes to disable the PLL condition-
ally, depending on whether the Bluetooth LLC
is in Sleep mode. The DHC bit and the CRC-
TRL.PLLPWD bit must be clear for this mech-
anism
automatically cleared when the device enters
Active mode.
0
1
Reserved
The Oscillating Low Frequency Clock bit indi-
cates whether the low-frequency oscillator is
producing a stable clock. When the low-fre-
quency oscillator is unavailable, the PMM will
not switch to Power Save, Idle, or Halt mode.
0
1
–
–
–
–
–
–
–
–
PLL is not disabled in Power Save mode,
unless disabled by the HCC mechanism
or the PLLPWD bit.
PLL is disabled in Power Save mode.
High-frequency oscillator is disabled in
Power Save or Idle mode only if the DMC
bit is set.
High-frequency oscillator is also disabled
if the Bluetooth LLC is idle.
PLL is disabled in Power Save or Idle
mode only if the DMC bit or the CRC-
TRL.PLLPWD bit is set.
PLL is also disabled if the Bluetooth LLC
is idle.
Low-frequency oscillator is unstable, dis-
abled, or not oscillating.
Low-frequency oscillator is available.
to
operate.
3
The
OHC OMC
2
HCCH
1
bit
OLC
0
is
59
OMC
OHC
12.7
Switching from a higher to a lower power consumption
mode is performed by writing an appropriate value to the
Power Management Control/Status Register (PMMCR).
Switching from a lower power consumption mode to the Ac-
tive mode is usually triggered by a hardware interrupt.
Figure 9 shows the four power consumption modes and the
events that trigger a transition from one mode to another.
Some of the power-up transitions are based on the occur-
rence of a wake-up event. An event of this type can be either
a maskable interrupt or a non-maskable interrupt (NMI). All
of the maskable hardware wake-up events are monitored by
the Multi-Input Wake-Up (MIWU) Module, which is active in
all modes. Once a wake-up event is detected, it is latched
until an interrupt acknowledge cycle occurs or a reset is ap-
plied.
A wake-up event causes a transition to the Active mode and
restores normal clock operation, but does not start execu-
tion of the program. It is the interrupt handler associated
Note:
HW Event = MIWU wake-up or NMI
WBPSM = 1 &
HAL T = 1 &
"WAIT"
WBPSM = 1 &
IDLE = 1 &
"WAIT"
Figure 9. Power Mode State Diagram
SWITCHING BETWEEN POWER MODES
The Oscillating Main Clock bit indicates
whether the high-frequency oscillator is pro-
ducing a stable clock. When the high-frequen-
cy oscillator is unavailable, the PMM will not
switch to Active mode.
0
1
The Oscillating High Frequency (PLL) Clock
bit indicates whether the PLL is producing a
stable clock. Because the PMM tests the sta-
bility of the PLL clock to qualify power mode
state transitions, a stable clock is indicated
when the PLL is disabled. This removes the
stability of the PLL clock from the test when
the PLL is disabled. When the PLL is enabled
but unstable, the PMM will not switch to Active
mode.
0
1
Reset
–
–
–
–
High-frequency oscillator is unstable, dis-
abled, or not oscillating.
High-frequency oscillator is available.
PLL is enabled but unstable.
PLL is stable or disabled (CRCTRL.PLL-
PWD = 0).
WBPSM = 0 & PSM = 1
or
WBPSM = 1 & PSM = 1 & "WAIT"
Power Save Mode
Active Mode
Idle Mode
Halt Mode
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HW Event
HW Event
HW Event
DS422