CP3BT10G38 National Semiconductor, CP3BT10G38 Datasheet - Page 149

• Manufacturer Part Number: CP3BT10G38
• Description: IC CPU RISC W/LLC&USB 100-LQFP
• Manufacturer: National Semiconductor

Specifications of CP3BT10G38

• Applications: Connectivity Processor
• Core Processor: CR16C
• Program Memory Type: FLASH (256 kB)
• Controller Series: CP3000
• Ram Size: 10K x 8
• Interface: Bluetooth, ACCESS.bus, Audio, UART, USB, Microwire/SPI
• Number Of I /o: 37
• Voltage - Supply: 2.25 V ~ 2.75 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *CP3BT10G38

23.5
Table 53 lists the CPU-accessible registers used to control
the Multi-Function Timers.
23.5.1
The TPRSC register is a byte-wide, read/write register that
holds the current value of the 5-bit clock prescaler (CLKPS).
This register is cleared on reset. The register format is
shown below.
CLKPS
7
TPRSC
TCNT1
TCNT2
TCTRL
TICLR
Name
TCKC
TCRA
TCRB
TICTL
Reserved
Table 53 Multi-Function Timer Registers
TIMER REGISTERS
Clock Prescaler Register (TPRSC)
The Clock Prescaler field specifies the divisor
used to generate the Timer Clock from the
System Clock. When the timer is configured to
use the prescaled clock, the System Clock is
divided by (CLKPS + 1) to produce the timer
clock. Therefore, the System Clock divisor
can range from 1 to 32.
5
FF FF4Ah
FF FF4Ch
FF FF4Eh
FF FF48h
FF FF40h
FF FF46h
FF FF42h
FF FF44h
FF FF50h
Address
4
CLKPS
Clock Unit Control
Reload/Capture A
Reload/Capture B
Timer/Counter 1
Timer/Counter 2
Control Register
Control Register
Clock Prescaler
Timer Interrupt
Timer Interrupt
Clear Register
Description
Timer Mode
Register
Register
Register
Register
Register
Register
0
149
23.5.2
The TCKC register is a byte-wide, read/write register that
selects the clock source for each timer/counter. Selecting
the clock source also starts the counter. This register is
cleared on reset, which disables the timer/counters. The
register format is shown below.
C1CSEL
C2CSEL
* Operation of the Slow Clock is determined by the CRC-
TRL.SCLK control bit, as described in Section 11.8.1.
23.5.3
The TCNT1 register is a word-wide, read/write register that
holds the current count value for Timer/Counter 1. The reg-
ister contents are not affected by a reset and are unknown
after power-up.
23.5.4
The TCNT2 register is a word-wide, read/write register that
holds the current count value for Timer/Counter 2. The reg-
ister contents are not affected by a reset and are unknown
after power-up.
15
15
Reserved
7
Clock Unit Control Register (TCKC)
Timer/Counter 1 Register (TCNT1)
Timer/Counter 2 Register (TCNT2)
6
The Counter 1 Clock Select field specifies the
clock mode for Timer/Counter 1 as follows:
000 – No clock (Timer/Counter 1 stopped,
001 – Prescaled System Clock.
010 – Reserved.
011 – Reserved.
100 – Slow Clock.*
101 – Reserved.
110 – Reserved.
111 – Reserved.
The Counter 2 Clock Select field specifies the
clock mode for Timer/Counter 2 as follows:
000 – No clock (Timer/Counter 2 stopped,
001 – Prescaled System Clock.
010 – Reserved.
011 – Reserved.
100 – Slow Clock*
101 – Reserved.
110 – Reserved.
111 – Reserved.
5
modes 1, 2, and 3 only).
modes 1, 2, and 3 only).
C2CSEL
TCNT1
TCNT2
3
2
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C1CSEL
0
0
0