CP3BT10G38 National Semiconductor, CP3BT10G38 Datasheet - Page 158

• Manufacturer Part Number: CP3BT10G38
• Description: IC CPU RISC W/LLC&USB 100-LQFP
• Manufacturer: National Semiconductor

Specifications of CP3BT10G38

• Applications: Connectivity Processor
• Core Processor: CR16C
• Program Memory Type: FLASH (256 kB)
• Controller Series: CP3000
• Ram Size: 10K x 8
• Interface: Bluetooth, ACCESS.bus, Audio, UART, USB, Microwire/SPI
• Number Of I /o: 37
• Voltage - Supply: 2.25 V ~ 2.75 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *CP3BT10G38

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IxCEN
IxDEN
24.2.5
The INTPND register is a word-wide read/write register
which contains all 16 interrupt pending bits. There are four
interrupt pending bits called IxAPD through IxDPD for each
timer subsystem. Each interrupt pending bit is set by a hard-
ware event and can be cleared if software writes a 1 to the
bit position. The value will remain unchanged if a 0 is written
to the bit position. All interrupt pending bits are cleared (0)
upon reset.
IxAPD
IxBPD
IxCPD
I2DPD I2CPD I2BPD I2APD I1DPD I1CPD I1BPD I1APD
I4DPD I4CPD I4BPD I4APD I3DPD I3CPD I3BPD I3APD
15
7
Interrupt Pending Register (INTPND)
14
6
The Timer x Interrupt C Enable bit controls in-
terrupt requests triggered on the correspond-
ing IxCPD bit being set. The associated
IxCPD bit will be updated regardless of the
value of the IxCEN bit.
0 – Disable system interrupt request for the
1 – Enable system interrupt request for the Ix-
Timer x Interrupt D Enable bit controls inter-
rupt requests triggered on the corresponding
IxDPD bit being set. The associated IxDPD bit
will be updated regardless of the value of the
IxDEN bit.
0 – Disable system interrupt request for the
1 – Enable system interrupt request for the
The Timer x Interrupt A Pending bit indicates
that an interrupt condition for the related timer
subsystem has occurred. Table 54 on page
155 lists the hardware condition which causes
this bit to be set.
0 – No interrupt pending.
1 – Timer interrupt condition occurred.
The Timer x Interrupt B Pending bit indicates
that an interrupt condition for the related timer
subsystem has occurred. Table 54 on page
155 lists the hardware condition which causes
this bit to be set.
0 – No interrupt pending.
1 – Timer interrupt condition occurred.
The Timer x Interrupt C Pending bit indicates
that an interrupt condition for the related timer
subsystem has occurred. Table 54 on page
155 lists the hardware condition which causes
this bit to be set.
0 – No interrupt pending.
1 – Timer interrupt condition occurred.
13
IxCPD pending bit.
CPD pending bit.
IxDPD pending bit.
IxDPD pending bit.
5
12
4
11
3
10
2
1
9
0
8
158
IxDPD
24.2.6
The CLK1PS register is a word-wide read/write register.
The register is split into two 8-bit fields called C1PRSC and
C2PRSC. Each field holds the 8-bit clock prescaler com-
pare value for timer subsystems 1 and 2 respectively. The
register is cleared at reset.
C1PRSC
C2PRSC
24.2.7
The Clock Prescaler Register 2 (CLK2PS) is a word-wide
read/write register. The register is split into two 8-bit fields
called C3PRSC and C4PRSC. Each field holds the 8-bit
clock prescaler compare value for timer subsystems 3 and
4 respectively. The register is cleared at reset.
C3PRSC
C4PRSC
15
15
Clock Prescaler Register 1 (CLK1PS)
Clock Prescaler Register 2 (CLK2PS)
C2PRSC
C4PRSC
The Timer x Interrupt D Pending bit indicates
that an interrupt condition for the related timer
subsystem has occurred. Table 54 on page
155 lists the hardware condition which causes
this bit to be set.
0 – No interrupt pending.
1 – Timer interrupt condition occurred.
The Clock Prescaler 1 Compare Value field
holds the 8-bit prescaler value for timer sub-
system 1. The counter of timer subsystem is
incremented each time when the clock pres-
caler compare value matches the value of the
clock prescaler counter. The division ratio is
equal to (C1PRSC + 1). For example, 00h is a
ratio of 1, and FFh is a ratio of 256.
The Clock Prescaler 2 Compare Value field
holds the 8-bit prescaler value for timer sub-
system 2. The counter of timer subsystem is
incremented each time when the clock pres-
caler compare value matches the value of the
clock prescaler counter. The division ratio is
equal to (C2PRSC + 1).
The Clock Prescaler 3 Compare Value field
holds the 8-bit prescaler value for timer sub-
system 3. The counter of timer subsystem is
incremented each time when the clock pres-
caler compare value matches the value of the
clock prescaler counter. The division ratio is
equal to (C3PRSC + 1).
The Clock Prescaler 4 Compare Value field
holds the 8-bit prescaler value for timer sub-
system 4. The counter of timer subsystem is
incremented each time when the clock pres-
caler compare value matches the value of the
clock prescaler counter. The division ratio is
equal to (C4PRSC + 1).
8
8
7
7
C1PRSC
C3PRSC
0
0