EVAL-AD5570EBZ Analog Devices Inc, EVAL-AD5570EBZ Datasheet - Page 6

• Manufacturer Part Number: EVAL-AD5570EBZ
• Description: 206-10G-01 Board I.c.
• Manufacturer: Analog Devices Inc
• Series: 0040r

Specifications of EVAL-AD5570EBZ

• Number Of Dac's: *
• Number Of Bits: 16
• Outputs And Type: 1, Single Ended
• Sampling Rate (per Second): 83k
• Data Interface: Serial
• Settling Time: 12µs
• Dac Type: *
• Voltage Supply Source: Dual ±
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD5570
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD5570
TIMING CHARACTERISTICS
DAISY-CHAINING AND READBACK
V
C
Table 3.
Parameter
f
t
t
t
t
t
t
t
t
t
t
t
1
2
3
MAX
1
2
3
4
5
6
7
8
9
10
14
All parameters guaranteed by design and characterization. Not production tested.
All input signals are measured with tr = tf = 5 ns (10% to 90% of V
With C
DD
L
LDAC
LDAC
3
SYNC
SCLK
= 200 pF to AGND; all specifications T
SDIN
SDO
= +12 V ± 5%, V
1
2
L
= 0 pF, t
NOTES
1
2
ASYNCHRONOUS LDAC UPDATE MODE.
SYNCHRONOUS LDAC UPDATE MODE.
1, 2
14
t
= 100 ns.
8
SS
t
4
= −12 V ± 5% or V
DB15 (N)
Limit at T
2
500
200
200
10
35
0
45
45
0
50
200
t
5
MIN
t
6
, T
MAX
DD
MIN
= +15 V ± 10%, V
to T
MAX
t
1
Figure 3. Daisy-Chaining Timing Diagram
, unless otherwise noted.
t
3
DD
Unit
MHz max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
) and timed from a voltage level of (V
DB0 (N)
SS
Rev. C | Page 6 of 24
= −15 V ± 10%, V
DB15 (N)
(N + 1)
DB15
Description
SCLK frequency
SCLK cycle time
SCLK high time
SCLK low time
SYNC to SCLK falling edge setup time
Data setup time
Data hold time
SCLK falling edge to SYNC rising edge
Minimum SYNC high time
SYNC rising edge to LDAC falling edge
LDAC pulse width
Data delay on SDO
t
2
REF
= 5 V, REFGND = AGND = DGND = 0 V, R
IL
+V
IH
)/2. SDO; R
DB0 (N)
PULLUP
(N + 1)
= 5 kΩ, C
DB0
t
7
(N + 1)
DB15
t
14
L
= 15 pF.
t
9
t
10
L
= 5 kΩ,