EVAL-AD5570EBZ Analog Devices Inc, EVAL-AD5570EBZ Datasheet - Page 16

• Manufacturer Part Number: EVAL-AD5570EBZ
• Description: 206-10G-01 Board I.c.
• Manufacturer: Analog Devices Inc
• Series: 0040r

Specifications of EVAL-AD5570EBZ

• Number Of Dac's: *
• Number Of Bits: 16
• Outputs And Type: 1, Single Ended
• Sampling Rate (per Second): 83k
• Data Interface: Serial
• Settling Time: 12µs
• Dac Type: *
• Voltage Supply Source: Dual ±
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD5570
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD5570
GENERAL DESCRIPTION
The AD5570 is a single 16-bit serial input, voltage output DAC. It
operates from supply voltages of ±11.4 V to ±16.5 V, and has a
buffered voltage output of up to ±13.6 V. Data is written to the
AD5570 in a 16-bit word format, via a 3-wire serial interface. The
device also offers an SDO pin, available for daisy-chaining or
readback.
The AD5570 incorporates a power-on reset circuit to ensure the
DAC output powers up to 0 V. The device also has a power-down
pin to reduce the typical current consumption to 16 μA.
DAC ARCHITECTURE
The DAC architecture of the AD5570 consists of a 16-bit, current-
mode, segmented R-2R DAC. The simplified circuit diagram for
the DAC section is shown in Figure 36.
The four MSBs of the 16-bit data word are decoded to drive
15 switches, E1 to E15. Each of these switches connects one
of the 15 matched resistors to either AGND or IOUT. The
remaining 12 bits of the data word drive switches S0 to S11
of the 12-bit R-2R ladder network.
V
REFERENCE BUFFERS
The AD5570 operates with an external reference. The reference
input (REFIN) has an input range of up to 7 V. This input voltage is
then used to provide a buffered positive and negative reference
for the DAC core. The positive reference is given by
and the negative reference to the DAC core is given by
These positive and negative reference voltages define the DAC
output range.
SERIAL INTERFACE
The AD5570 is controlled over a versatile 3-wire serial interface
that operates at clock rates up to 10 MHz and is compatible with
SPI, QSPI, MICROWIRE, and DSP interface standards.
Input Shift Register
The input shift register is 16 bits wide. Data is loaded into the
device as a 16-bit word under the control of a serial clock input,
SCLK. The timing diagram for this operation is shown in Figure 2.
REF
E15
+
−
4 MSBs DECODED INTO
15 EQUAL SEGMENTS
V
V
REF
REF
2R
E14
=
=
2R
2
2
×
×
V
V
E1
Figure 36. DAC Ladder Structure
REFIN
REFIN
2R
R
S11
12-BIT R-2R LADDER
2R
R
S10
2R
R
S0
2R
2R
AGND
IOUT
R/8
V
OUT
Rev. C | Page 16 of 24
On power-up, the input shift register and DAC register are
loaded with midscale (0x8000). The DAC coding is straight
binary; all 0s produce an output of −2 V
output of +2 V
The SYNC input is a level-triggered input that acts as a frame
synchronization signal and chip enable. SYNC must frame the
serial word being loaded into the device. Data can be transferred
into the device only while SYNC is low. To start the serial data
transfer, SYNC is taken low, observing the minimum SYNC to
SCLK falling edge setup time, t
on SDIN is shifted into the device’s input shift register on the
falling edges of SCLK. SYNC can be taken high after the falling
edge of the 16
falling edge to SYNC rising edge time, t
After the end of the serial data transfer, data is automatically
transferred from the input shift register to the input register
of the DAC.
When data has been transferred into the input register of the DAC,
the DAC register and DAC output can be updated by taking
LDAC low while SYNC is high.
Load DAC Input ( LDAC )
There are two ways that the DAC register and DAC output can
be updated when data has been transferred into the input register
of the DAC. Depending on the status of both SYNC and LDAC ,
one of two update modes is selected.
The first mode is synchronous LDAC . In this mode, LDAC is low
while data is being clocked into the input shift register. The DAC
output is updated when SYNC is taken high. The update here
occurs on the rising edge of SYNC .
The second mode is asynchronous LDAC . In this mode, LDAC
is high while data is being clocked in. The DAC output is updated
by taking LDAC low any time after SYNC has been taken high.
The update now occurs on the falling edge of LDAC .
Figure 37 shows a simplified block diagram of the input loading
circuitry.
Figure 37. Simplified Serial Interface Showing Input Loading Circuitry
V
REFIN
LDAC
SYNC
SDIN
th
REF
SCLK pulse, observing the minimum SCLK
− 1 LSB.
INPUT SHIFT
REGISTER
REGISTER
16-BIT
DAC
DAC
4
. After SYNC goes low, serial data
I/V AMPLIFIER
OUTPUT
7
REF
.
SDO
; all 1s produce an
V
OUT