EVAL-AD5570EBZ Analog Devices Inc, EVAL-AD5570EBZ Datasheet - Page 5

• Manufacturer Part Number: EVAL-AD5570EBZ
• Description: 206-10G-01 Board I.c.
• Manufacturer: Analog Devices Inc
• Series: 0040r

Specifications of EVAL-AD5570EBZ

• Number Of Dac's: *
• Number Of Bits: 16
• Outputs And Type: 1, Single Ended
• Sampling Rate (per Second): 83k
• Data Interface: Serial
• Settling Time: 12µs
• Dac Type: *
• Voltage Supply Source: Dual ±
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD5570
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TIMING CHARACTERISTICS
STANDALONE
V
C
Table 2.
Parameter
f
t
t
t
t
t
t
t
t
t
t
t
t
t
1
2
MAX
1
2
3
4
5
6
7
8
9
10
11
12
13
All parameters guaranteed by design and characterization. Not production tested.
All input signals are measured with tr = tf = 5 ns (10% to 90% of V
L
DD
= 200 pF to AGND; all specifications T
= +12 V ± 5%, V
LDAC
LDAC
SCLK
SYNC
SDIN
CLR
NOTES
1
2
ASYNCHRONOUS LDAC UPDATE MODE. UPDATE ON FALLING EDGE OF LDAC.
SYNCHRONOUS LDAC UPDATE MODE. UPDATE ON RISING EDGE OF SYNC.
2
1
1, 2
t
8
SS
Limit at T
10
100
35
35
10
35
0
45
45
0
50
0
0
20
= −12 V ± 5% or V
t
4
DB15
MIN
, T
t
5
MAX
t
6
DD
MIN
t
= +15 V ± 10%, V
11
to T
Unit
MHz max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
MAX
Figure 2. Serial Interface Timing Diagram
t
, unless otherwise noted.
2
DD
) and timed from a voltage level of (V
SS
Rev. C | Page 5 of 24
= −15 V ± 10%, V
t
1
t
3
Description
SCLK frequency
SCLK cycle time
SCLK high time
SCLK low time
SYNC to SCLK falling edge setup time
Data setup time
Data hold time
SCLK falling edge to SYNC rising edge
Minimum SYNC high time
SYNC rising edge to LDAC falling edge
LDAC pulse width
LDAC falling edge to SYNC falling edge (no update)
LDAC rising edge to SYNC rising edge (no update)
CLR pulse width
DB0
t
7
t
9
REF
= 5 V, REFGND = AGND = DGND = 0 V, R
t
12
t
10
IL
+V
IH
)/2.
t
13
L
= 5 kΩ,
AD5570