EVAL-AD5570EBZ Analog Devices Inc, EVAL-AD5570EBZ Datasheet - Page 21

• Manufacturer Part Number: EVAL-AD5570EBZ
• Description: 206-10G-01 Board I.c.
• Manufacturer: Analog Devices Inc
• Series: 0040r

Specifications of EVAL-AD5570EBZ

• Number Of Dac's: *
• Number Of Bits: 16
• Outputs And Type: 1, Single Ended
• Sampling Rate (per Second): 83k
• Data Interface: Serial
• Settling Time: 12µs
• Dac Type: *
• Voltage Supply Source: Dual ±
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD5570
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

MICROPROCESSOR INTERFACING
Microprocessor interfacing to the AD5570 is via a serial bus
that uses standard protocol compatible with microcontrollers
and DSP processors. The communications channel is a 3-wire
(minimum) interface consisting of a clock signal, a data signal,
and a synchronization signal. The AD5570 requires a 16-bit
data word with data valid on the falling edge of SCLK.
For all the interfaces, the DAC output update can be done auto-
matically when all the data is clocked in, or it can be done under
the control of LDAC . The contents of the DAC register can be
read using the readback function.
AD5570 to MC68HC11 Interface
Figure 42 shows an example of a serial interface between the
AD5570 and the MC68HC11 microcontroller. The serial periph-
eral interface (SPI) on the MC68HC11 is configured for master
mode (MSTR = 1), clock polarity bit (CPOL = 0), and the clock
phase bit (CPHA = 1). The SPI is configured by writing to the SPI
control register (SPCR); see documentation on the MC68HC11.
SCK of the MC68HC11 drives the SCLK of the AD5570, the
MOSI output drives the serial data line (SDIN) of the AD5570,
and the MISO input is driven from SDO. The SYNC is driven
from one of the port lines, in this case, PC7.
When data is being transmitted to the AD5570, the SYNC line
(PC7) is taken low and data is transmitted MSB first. Data appear-
ing on the MOSI output is valid on the falling edge of SCK. Eight
falling clock edges occur in the transmit cycle; therefore, in order
to load the required 16-bit word, PC7 is not brought high until
the second 8-bit word has been transferred to the DACs input
shift register.
*ADDITIONAL PINS OMITTED FOR CLARITY.
MC68HC11*
Figure 42. AD5570 to MC68HC11 Interface
SCLK
MISO
MOSI
PC7
SDO
SDIN
SCLK
SYNC
AD5570*
Rev. C | Page 21 of 24
LDAC is controlled by the PC6 port output. The DAC can be
updated after each 2-byte transfer by bringing LDAC low. This
example does not show other serial lines for the DAC. If CLR
were used, control it by the Port Output PC5.
AD5570 to 8xC51 Interface
The AD5570 requires a clock synchronized to the serial data. For
this reason, the 8xC51 must be operated in Mode 0. In this mode,
serial data enters and exits through RxD, and a shift clock is
output on TxD.
P3.3 and P3.4 are bit-programmable pins on the serial port and
are used to drive SYNC and LDAC , respectively.
The 8xC51 provides the LSB of its SBUF register as the first bit
in the data stream. The user must ensure that the data in the SBUF
register is arranged correctly because the DAC expects MSB first.
When data is to be transmitted to the DAC, P3.3 is taken low. Data
on RxD is clocked out of the microcontroller on the rising edge
of TxD and is valid on the falling edge. As a result, no glue logic
is required between this DAC and the microcontroller interface.
The 8xC51 transmits data in 8-bit bytes with only eight falling
clock edges occurring in the transmit cycle. Because the DAC
expects a 16-bit word, SYNC (P3.3) must be left low after the first
eight bits are transferred. After the second byte has been trans-
ferred, the P3.3 line is taken high. The DAC can be updated using
LDAC via P3.4 of the 8xC51.
*ADDITIONAL PINS OMITTED FOR CLARITY.
8xC51*
Figure 43. AD5570 to 8xC51 Interface
P3.3
P3.4
RxD
TxD
SDIN
SCLK
SYNC
LDAC
AD5570*
AD5570