EP2SGX90EF1152I4 Altera, EP2SGX90EF1152I4 Datasheet - Page 39

• Manufacturer Part Number: EP2SGX90EF1152I4
• Description: Stratix II GX
• Manufacturer: Altera

Specifications of EP2SGX90EF1152I4

• Family Name: Stratix II GX
• Number Of Logic Blocks/elements: 90960
• # I/os (max): 558
• Frequency (max): 732.1MHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 90960
• Ram Bits: 4520448
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FC-FBGA
• Lead Free Status / Rohs Status: Not Compliant

Figure 2–24. Stratix II GX Block in Serial Loopback Mode with BIST and PRBS
Altera Corporation
October 2007
FPGA
Logic
Array
Transmitter Digital Logic
Receiver Digital Logic
Incremental
Incremental
Generator
RX Phase
Compen-
Verify
BIST
BIST
sation
FIFO
Compensation
TX Phase
FIFO
Ordering
Serializer
Byte
Byte
Figure 2–24
Parallel Loopback
The parallel loopback mode exercises the digital logic portion of the
transceiver data path. The analog portions are not used in this loopback
path, and the received high-speed serial data is not retimed. This protocol
is available as one of the sub-protocols under Basic mode and can be used
only for Basic double-width mode.
In this loopback mode, the data from the internally available BIST
generator is transmitted. The data is looped back after the end of PCS and
before the PMA. On the receive side, an internal BIST verifier checks for
errors. This loopback enables you to verify the PCS block.
20
serializer
Byte
De-
Encoder
8B/10B
shows the data path in serial loopback mode.
Generator
PRBS
BIST
Decoder
8B/10B
Match
Rate
FIFO
Stratix II GX Device Handbook, Volume 1
Deskew
FIFO
PRBS
Verify
BIST
Aligner
Word
Stratix II GX Architecture
Analog Receiver and
Transmitter Logic
Serializer
serializer
De-
Recovery
Loopback
Clock
Serial
Unit
2–31