EP2SGX90EF1152I4 Altera, EP2SGX90EF1152I4 Datasheet - Page 153

• Manufacturer Part Number: EP2SGX90EF1152I4
• Description: Stratix II GX
• Manufacturer: Altera

Specifications of EP2SGX90EF1152I4

• Family Name: Stratix II GX
• Number Of Logic Blocks/elements: 90960
• # I/os (max): 558
• Frequency (max): 732.1MHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 90960
• Ram Bits: 4520448
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FC-FBGA
• Lead Free Status / Rohs Status: Not Compliant

Altera Corporation
October 2007
Table 2–42. Document Revision History (Part 3 of 6)
Document
Date and
Version
Moved the “Transmit State Machine” section to
after the “8B/10B Encoder” section.
Moved the “PCI Express Receiver Detect” and
“PCI Express Electric Idles (or Individual
Transmitter Tri-State)” sections to after the
“Transmit Buffer” section.
Moved the “Dynamic Reconfiguration” section
to the “Other Transceiver Features” section.
Moved the “Calibration Block”, “Receiver PLL
& CRU”, and “Deserializer (Serial-to-Parallel
Converter)” sections to the “Receiver Path”
section.
Moved the “8B/10B Decoder” and “Receiver
State Machine” sections to after the “Rate
Matcher” section.
Moved the “Byte Ordering Block” section to
after the “Byte Deserializer” section.
Updated the Clocking diagrams.
Added the “Clock Resource for PLD-
Transceiver Interface” section.
Added the “On-Chip Parallel Termination with
Calibration” section to the “On-Chip
Termination” section.
Updated:
●
●
●
●
●
●
●
●
●
●
Updated Figures 2–3, 2–9, 2–24, 2–25, 2–28,
2–29, 2–60, 2–62.
Change 622 Mbps to 600 Mbps throughout the
chapter.
Table 2–2.
Table 2–10
Table 2–14.
Table 2–3.
Table 2–5.
Table 2–8.
Table 2–13
Table 2–18
Table 2–19
Table 2–29.
Changes Made
Stratix II GX Device Handbook, Volume 1
Summary of Changes
Stratix II GX Architecture
2–145