EP2SGX90EF1152I4 Altera, EP2SGX90EF1152I4 Datasheet - Page 101

Stratix II GX

EP2SGX90EF1152I4

Manufacturer Part Number
EP2SGX90EF1152I4
Description
Stratix II GX
Manufacturer
Altera
Datasheet

Specifications of EP2SGX90EF1152I4

Family Name
Stratix II GX
Number Of Logic Blocks/elements
90960
# I/os (max)
558
Frequency (max)
732.1MHz
Process Technology
SRAM
Operating Supply Voltage (typ)
1.2V
Logic Cells
90960
Ram Bits
4520448
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
1152
Package Type
FC-FBGA
Lead Free Status / Rohs Status
Not Compliant

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0
Figure 2–65. EP2SGX30 Device I/O Clock Groups
Altera Corporation
October 2007
IO_CLKH[7..0]
IO_CLKG[7..0]
8
8
8
IOE clocks have row and column block regions that are clocked by 8 I/O
clock signals chosen from the 24 quadrant clock resources.
and
the Quadrant
the Quadrant
24 Clocks in
24 Clocks in
2–66
IO_CLKA[7..0]
IO_CLKF[7..0]
show the quadrant relationship to the I/O clock regions.
8
IO_CLKB[7..0]
IO_CLKE[7..0]
8
the Quadrant
the Quadrant
24 Clocks in
24 Clocks in
Stratix II GX Device Handbook, Volume 1
8
Stratix II GX Architecture
8
8
Figures 2–65
I/O Clock Regions
IO_CLKC[7..0]
IO_CLKD[7..0]
2–93

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