DSPIC33FJ128GP804-H/PT Microchip Technology, DSPIC33FJ128GP804-H/PT Datasheet - Page 74

• Manufacturer Part Number: DSPIC33FJ128GP804-H/PT
• Description: 16-bit DSC, 128KB Flash, CAN, DMA, 40 MIPS, NanoWatt 44 TQFP 10x10x1mm TRAY
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ128GP804-H/PT

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 13x10b/12b, D/A 6x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 140°C
• Package / Case: 44-TQFP
• Processor Series: dsPIC33F
• Core: dsPIC
• Data Bus Width: 16 bit
• Interface Type: SPI, I2C, UART, JTAG
• Number Of Programmable I/os: 35
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 140 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPLAB IDE Software
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 13 Channel
• A/d Bit Size: 10 bit
• A/d Channels Available: 13
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
5.2
The dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/
X04, and dsPIC33FJ128GPX02/X04 Flash program
memory array is organized into rows of 64 instructions
or 192 bytes. RTSP allows the user application to erase
a page of memory, which consists of eight rows (512
instructions) at a time, and to program one row or one
word at a time.
programming times. The 8-row erase pages and single
row write rows are edge-aligned from the beginning of
program memory, on boundaries of 1536 bytes and
192 bytes, respectively.
The program memory implements holding buffers that
can contain 64 instructions of programming data. Prior
to the actual programming operation, the write data
must be loaded into the buffers sequentially. The
instruction words loaded must always be from a group
of 64 boundary.
The basic sequence for RTSP programming is to set up
a Table Pointer, then do a series of TBLWT instructions
to load the buffers. Programming is performed by
setting the control bits in the NVMCON register. A total
of 64 TBLWTL and TBLWTH instructions are required
to load the instructions.
All of the table write operations are single-word writes
(two instruction cycles) because only the buffers are
written.
programming each row.
5.3
A complete programming sequence is necessary for
programming or erasing the internal Flash in RTSP
mode.
programming operation is finished.
The programming time depends on the FRC accuracy
(see
Tuning register (see
Equation 5-1
values for the Row Write Time, Page Erase Time and
Word Write Cycle Time parameters (see
EQUATION 5-1:
DS70292E-page 74
--------------------------------------------------------------------------------------------------------------------------- -
7.37 MHz
Table
The
RTSP Operation
Programming Operations
A
30-19) and the value of the FRC Oscillator
×
programming
to calculate the minimum and maximum
processor
(
FRC Accuracy
Table 30-12
Register
PROGRAMMING TIME
T
stalls
shows typical erase and
cycle
)%
9-4). Use the formula in
×
(waits)
(
FRC Tuning
is
Table
required
until
30-12).
)%
the
for
For example, if the device is operating at +125°C,
the FRC accuracy will be ±5%. If the TUN<5:0> bits
(see
minimum row write time is equal to
EQUATION 5-2:
The maximum row write time is equal to
EQUATION 5-3:
Setting the WR bit (NVMCON<15>) starts the
operation, and the WR bit is automatically cleared
when the operation is finished.
5.4
Two SFRs are used to read and write the program
Flash memory: NVMCON and NVMKEY.
The NVMCON register
blocks are to be erased, which memory type is to be
programmed and the start of the programming cycle.
NVMKEY
used for write protection. To start a programming or
erase sequence, the user application must consecu-
tively write 0x55 and 0xAA to the NVMKEY register.
Refer to
further details.
T
T
RW
RW
=
=
Register
----------------------------------------------------------------------------------------------- - 1.586ms
7.37 MHz
----------------------------------------------------------------------------------------------- - 1.435ms
7.37 MHz
Control Registers
Section 5.3 “Programming Operations”
(Register
9-4) are set to ‘b111111, the
×
×
(
(
11064 Cycles
11064 Cycles
1 0.05
5-2) is a write-only register that is
1
–
+
MINIMUM ROW WRITE
TIME
MAXIMUM ROW WRITE
TIME
0.05
© 2011 Microchip Technology Inc.
(Register
)
)
×
×
(
(
1 0.00375
1 0.00375
–
–
5-1) controls which
Equation
Equation
)
)
=
=
5-2.
5-3.
for