DSPIC33FJ128GP804-H/PT Microchip Technology, DSPIC33FJ128GP804-H/PT Datasheet - Page 231

• Manufacturer Part Number: DSPIC33FJ128GP804-H/PT
• Description: 16-bit DSC, 128KB Flash, CAN, DMA, 40 MIPS, NanoWatt 44 TQFP 10x10x1mm TRAY
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ128GP804-H/PT

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 13x10b/12b, D/A 6x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 140°C
• Package / Case: 44-TQFP
• Processor Series: dsPIC33F
• Core: dsPIC
• Data Bus Width: 16 bit
• Interface Type: SPI, I2C, UART, JTAG
• Number Of Programmable I/os: 35
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 140 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPLAB IDE Software
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 13 Channel
• A/d Bit Size: 10 bit
• A/d Channels Available: 13
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

REGISTER 19-8:
REGISTER 19-9:
© 2011 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-8
bit 7-0
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-8
bit 7-6
bit 5-0
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
R/W-0
R-0
R-0
U-0
—
SJW<1:0>
TERRCNT<7:0>: Transmit Error Count bits
RERRCNT<7:0>: Receive Error Count bits
Unimplemented: Read as ‘0’
SJW<1:0>: Synchronization Jump Width bits
11 = Length is 4 x T
10 = Length is 3 x T
01 = Length is 2 x T
00 = Length is 1 x T
BRP<5:0>: Baud Rate Prescaler bits
11 1111 = T
•
•
•
00 0010 = T
00 0001 = T
00 0000 = T
R/W-0
R-0
R-0
U-0
—
CiEC: ECAN™ TRANSMIT/RECEIVE ERROR COUNT REGISTER
CiCFG1: ECAN™ BAUD RATE CONFIGURATION REGISTER 1
Q
Q
Q
Q
C = Writable bit, but only ‘0’ can be written to clear the bit
W = Writable bit
‘1’ = Bit is set
W = Writable bit
‘1’ = Bit is set
= 2 x 64 x 1/F
= 2 x 3 x 1/F
= 2 x 2 x 1/F
= 2 x 1 x 1/F
R/W-0
R-0
R-0
U-0
—
Q
Q
Q
Q
CAN
CAN
CAN
CAN
R/W-0
R-0
R-0
U-0
RERRCNT<7:0>
TERRCNT<7:0>
—
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-0
R-0
R-0
U-0
—
BRP<5:0>
R/W-0
R-0
R-0
U-0
—
x = Bit is unknown
x = Bit is unknown
R/W-0
R-0
R-0
U-0
—
DS70292E-page 231
R/W-0
R-0
R-0
U-0
—
bit 8
bit 0
bit 8
bit 0