CY7C68001-56LFXC Cypress Semiconductor Corp, CY7C68001-56LFXC Datasheet - Page 44

• Manufacturer Part Number: CY7C68001-56LFXC
• Description: IC,Bus Controller,LLCC,56PIN
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr
• Type: USBr

Specifications of CY7C68001-56LFXC

• Protocol: USB 2.0
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 56-VQFN Exposed Pad, 56-HVQFN, 56-SQFN, 56-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 428-1942; CY7C68001-56LFXC

Document #: 38-08013 Rev. *J
Description Title: CY7C68001 EZ-USB SX2™ High Speed USB Interface Device
Document Number: 38-08013
*D
*G
*H
*E
*F
*J
*I
2665531
2733374
130447
243316
329238
392570
411515
02/26/2009
07/08/2009
See ECN
See ECN
See ECN
See ECN
12/17/03
ANTG/AESA Updated cross-references on pages 2 and 3
DPT/PYRS Added package diagram (51-85187) and updated Ordering Information table.
KKU
KKU
KEV
KEV
BHA
Provided additional timing restrictions and requirement regarding the use of
Modified
Replaced package diagram in
Fixed last history entry for rev *C
Change reference in section 2.7.2.4 from XXXXXXX to 7.3
Removed the word “compatible” in section 3.3
Change the text in section 5.0, last paragraph from 0xE6FB to 0xE683
Changed label “Reset” to “Default” in sections 5.1 and 7.2 through 7.14
Reformatted Figure 4
Added entries 3A, 3B, 3C, 0xE609, and 0xE683 to
Change access on hex values 07 and 09 from bbbbbbbb to bbbbrbrr
Removed t
Corrected timing diagrams, figures 11-1,11-2, 11-6
Changed
reference to t3 which should be t2, added reference of t3 for deasserting SLWR and
reworded section 11.6
Updated I
Reformatted data sheet to latest format
Added Lead-free parts numbers
Updated default value for address 0x07 and 0x09
Added Footnote 3.
Removed requirement of less then 360 nsec period between nibble writes in
command
Changed PKTEND to FLAGS output propagation delay in table 11-16 from a max
value of 70 ns to 110 ns
PKTEND pin to commit a short one byte/word packet subsequent to committing a
packet automatically (when in auto mode)
Miscellaneous grammar corrections.
Added 3.4.3 section header.
Fixed command sequence step 3 to say register value instead of High Byte of
Register Address (upper and lower nibble in two places).
Removed statement that programmable flag polarity is set to active low and cannot
be altered. Programmable flag relies on DECIS bit settings.
Updated Amkor application note URL.
Changed T
Changed T
Changed FLAGS Interrupt from empty to not-empty to both empty to not-empty and
from not-empty to empty conditions for triggering this interrupt.
Changed corporate address to 198 Champion Court.
Added information in section
enumeration.
Updated template
Updated section numbers
Figure 5-1.
Figure 13-16.
CC
XFD
XINT
RDY
typical and maximum values
from
in Figure 11-4 to be from deassertion edge of SLWR.
in Figure 11-3 to be from deassertion edge of SLRD.
Figure 13-9.
to fit across columns. It was getting cropped in half.
through
USB Signaling Speed
Figure 18-2.
Figure 13-21.
and
Figure 13-10.
spec number 51-85144 with clear image
for clarity, text which followed had
Figure 9-1
on page 2 on Full Speed only
and tables 11-1,2, and 5
CY7C68001
Page 44 of 45
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