CY7C68001-56LFXC Cypress Semiconductor Corp, CY7C68001-56LFXC Datasheet - Page 22

• Manufacturer Part Number: CY7C68001-56LFXC
• Description: IC,Bus Controller,LLCC,56PIN
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr
• Type: USBr

Specifications of CY7C68001-56LFXC

• Protocol: USB 2.0
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 56-VQFN Exposed Pad, 56-HVQFN, 56-SQFN, 56-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 428-1942; CY7C68001-56LFXC

9.9 EPxxFLAGS Registers 0x1E–0x1F
The EPxxFLAGS provide an alternate way of checking the status
of the endpoint FIFO flags. If enabled, the SX2 can interrupt the
external master when a flag is asserted, and the external master
can read these two registers to determine the state of the FIFO
flags. If the INFM1 and/or OEP1 bits are set, then the EPxEF and
EPxFF bits are actually empty +1 and full –1.
9.9.1 EPxPF Bit 6, Bit 2
This bit is the current state of endpoint x’s programmable flag.
9.9.2 EPxEF Bit 5, Bit 1
This bit is the current state of endpoint x’s empty flag. EPxEF =
1 if the endpoint is empty.
9.9.3 EPxFF Bit 4, Bit 0
This bit is the current state of endpoint x’s full flag. EPxFF = 1 if
the endpoint is full.
9.10 INPKTEND/FLUSH Register 0x20
This register allows the external master to duplicate the function
of the PKTEND pin. The register also allows the external master
to selectively flush endpoint FIFO buffers.
Bit [4..7]: FIFOx
These bits allows the external master to selectively flush any or
all of the endpoint FIFOs. By writing the desired endpoint FIFO
bit, SX2 logic flushes the selected FIFO. For example setting bit
7 flushes endpoint 8 FIFO.
Bit [3..0]: EPx
These bits are is used only for IN transfers. By writing the desired
endpoint number (2,4,6 or 8), SX2 logic automatically commits
an IN buffer to the USB host. For example, for committing a
packet through endpoint 6, set the lower nibble to 6: set bits 1
and 2 high.
Document #: 38-08013 Rev. *J
EP24FLAGS
EP68FLAGS
INPKTEND/FLUSH
Bit #
Bit Name
Read/Write
Default
Bit #
Bit Name
Read/Write
Default
Bit #
Bit Name
Read/Write
Default
FIFO8 FIFO6 FIFO4 FIFO2
R/W
R/W
W
7
0
7
0
0
7
0
0
EP4PF EP4EF EP4FF
EP8PF EP8EF EP8FF
R/W
R/W
W
6
0
6
0
6
0
R/W
R/W
W
5
0
5
1
5
1
R/W
R/W
W
4
0
4
0
4
0
R/W
R/W
EP3
3
0
0
3
0
0
W
3
0
EP2PF EP2EF EP2FF
EP6PF EP6EF EP6FF
R/W
R/W
2
0
2
0
EP2
W
2
0
R/W
R/W
EP1
1
1
1
1
W
1
0
R/W
R/W
EP0
0x1E
0x1F
0x20
0
0
0
0
W
0
0
9.11 USBFRAMEH/L Registers 0x2A, 0x2B
Every millisecond, the USB host sends an SOF token indicating
“Start Of Frame,” along with an 11-bit incrementing frame count.
The SX2 copies the frame count into these registers at every
SOF.
One use of the frame count is to respond to the USB
SYNC_FRAME Request. If the SX2 detects a missing or garbled
SOF, the SX2 generates an internal SOF and increments
USBFRAMEL–USBRAMEH.
9.12 MICROFRAME Registers 0x2C
MICROFRAME contains a count 0–7 that indicates which of the
125 microsecond microframes last occurred.
This register is active only when SX2 is operating in high speed
mode (480 Mbits/sec).
9.13 FNADDR Register 0x2D
During the USB enumeration process, the host sends a device
a unique 7-bit address that the SX2 copies into this register.
There is normally no reason for the external master to know its
USB device address because the SX2 automatically responds
only to its assigned address.
Bit 7: HSGRANT, Set to 1 if the SX2 enumerated at high speed.
Set to 0 if the SX2 enumerated at full speed.
Bit[6..0]: Address set by the host.
USBFRAMEH
USBFRAMEL
MICROFRAME
FNADDR
Bit #
Bit Name
Read/Write
Default
Bit #
Bit Name
Read/Write
Default
Bit #
Bit Name
Read/Write
Default
Bit #
Bit Name
Read/Write
Default
HSGRANT
FC7
R
X
7
0
R
X
7
R
X
7
0
R
7
0
FC6
R
X
6
0
R
X
6
R
6
0
X
FA6
R
6
0
FC5
R
X
5
0
5
R
X
5
0
R
X
FA5
R
5
0
FC4
R
X
4
0
R
4
X
R
X
4
0
FA4
R
4
0
FC3
3
0
R
X
R
X
3
FA3
R
X
3
0
R
3
0
CY7C68001
MF2
FC2
FC10
2
R
X
R
X
2
FA2
R
X
2
R
2
0
Page 22 of 45
MF1
FC1
R
FA1
1
X
FC9
R
X
1
R
1
0
R
X
1
MF0
0x2C
0x2D
FC0
FA0
0x2B
R
0
FC8
x
R
0
R
X
0
0
0x2A
R
0
x
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