CY7C68001-56LFXC Cypress Semiconductor Corp, CY7C68001-56LFXC Datasheet - Page 16

• Manufacturer Part Number: CY7C68001-56LFXC
• Description: IC,Bus Controller,LLCC,56PIN
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr
• Type: USBr

Specifications of CY7C68001-56LFXC

• Protocol: USB 2.0
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 56-VQFN Exposed Pad, 56-HVQFN, 56-SQFN, 56-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 428-1942; CY7C68001-56LFXC

Table 9-1. SX2 Register Summary (continued)
Document #: 38-08013 Rev. *J
2E
30
31
32
33
3A
3B
3C
Address
0xE609
0xE683
Notes
Hex Size
8.
9. Please note that the SX2 was not designed to support dynamic modification of these endpoint configuration registers. If your applications need the ability to
10. Please note that the SX2 was not designed to support dynamic modification of the INPKTEND/FLUSH register. If your applications need the ability to change
change endpoint configurations after the device has already enumerated with a specific configuration, please expect some delay in being able to access the
FIFOs after changing the configuration. For example, after writing to EP2PKTLENH, you must wait for at least 35 μs measured from the time the READY signal
is asserted before writing to the FIFO. This delay time varies for different registers and is not characterized, because the SX2 was not designed for this dynamic
change of endpoint configuration registers.
endpoint configurations or access the INPKTEND register after the device has already enumerated with a specific configuration, please expect some delay in
being able to access the FIFOs after changing this register. After writing to INPKTEND/FLUSH, you must wait for at least 85 μs measured from the time the
READY signal is asserted before writing to the FIFO. This delay time varies for different registers and is not characterized, because the SX2 was not designed
for this dynamic change of endpoint configuration registers.
1
500 DESC
64
8/1
1
1
1
1
INTENABLE Interrupt Enable
Descriptor
Endpoint 0
EP0BUF
SETUP
EP0BC
Un-Indexed Register control
Un-Indexed Registers in XDATA Space
FIFOPIN-
POLAR
TOGCTL
Name
Descriptor RAM
Endpoint 0 Buffer
Endpoint 0 Setup Data / Stall
Endpoint 0 Byte Count
Un-Indexed Register Low Byte
pointer
Un-Indexed Register High
Byte pointer
Un-Indexed Register Data
FIFO Interface Pins Polarity
Data Toggle Control
Description
SETUP
D7
d7
d7
d7
d7
a7
a7
d7
Q
0
EP0BUF
D6
d6
d6
d6
d6
a6
a6
d6
S
0
PKTEND
FLAGS
D5
d5
d5
d5
d5
a5
a5
d5
R
SLOE
D4
d4
d4
d4
d4
a4
a4
d4
IO
1
SLRD
EP3
D3
d3
d3
d3
d3
a3
a3
d3
1
ENUMOK
SLWR
EP2
D2
d2
d2
d2
d2
a2
a2
d2
BUSAC-
TIVITY
EP1
D1
EF
d1
d1
d1
d1
a1
a1
d1
READY
EP0
D0
d0
d0
d0
d0
a0
a0
d0
FF
CY7C68001
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11111111 bbbbbbbb
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