CY7C68001-56LFXC Cypress Semiconductor Corp, CY7C68001-56LFXC Datasheet - Page 36

• Manufacturer Part Number: CY7C68001-56LFXC
• Description: IC,Bus Controller,LLCC,56PIN
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr
• Type: USBr

Specifications of CY7C68001-56LFXC

• Protocol: USB 2.0
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 56-VQFN Exposed Pad, 56-HVQFN, 56-SQFN, 56-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 428-1942; CY7C68001-56LFXC

Figure 13-20.
FIFO signals during an asynchronous FIFO read. It shows a
single read followed by a burst read.
■
■
■
Figure 13-21.
FIFO write in an asynchronous mode. The diagram shows a
single write followed by a burst write of 3 bytes and committing
the 4-byte-short packet using PKTEND.
■
■
■
■
Document #: 38-08013 Rev. *J
At t = 0 the FIFO address is stable and the SLCS signal is
asserted.
At t = 1, SLOE is asserted. This results in the data bus being
driven. The data that is driven on to the bus is previous data,
it data that was in the FIFO from a prior read cycle.
At t = 2, SLRD is asserted. The SLRD must meet the minimum
active pulse of t
t
SLRD or before SLRD is asserted (that is, the SLCS and SLRD
signals must both be asserted to start a valid read condition).
At t = 0 the FIFO address is applied, insuring that it meets the
setup time of t
(SLCS may be tied low in some applications).
At t = 1 SLWR is asserted. SLWR must meet the minimum
active pulse of t
t
before SLWR is asserted.
At t = 2, data must be present on the bus t
deasserting edge of SLWR.
At t = 3, deasserting SLWR causes the data to be written from
the data bus to the FIFO and then increments the FIFO pointer.
RDpwh
WRpwh
FIFOADR
PKTEND
FLAGS
FIFO DATA BUS Not Driven
FIFO POINTER
SLWR
DATA
SLCS
. If SLCS is used then, SLCS must be asserted with
. If the SLCS is used, it must be asserted with SLWR or
diagrams the timing relationship of the SLAVE
diagrams the timing relationship of the SLAVE
t=0
SFA
RDpwl
WRpwl
t
SFA
. If SLCS is used, it must also be asserted
t =1
N
Figure 13-21. Slave FIFO Asynchronous Write Sequence and Timing Diagram
and minimum de-active pulse width of
t
and minimum de-active pulse width of
WRpwl
t=2
Figure 13-20. Slave FIFO Asynchronous Read Sequence of Events Diagram
t
SFD
SLOE
t=3
N
t
t
FDH
WRpwh
t
Driven: X
FAH
t
XFLG
N
SLRD
SFD
T=0
N
N
t
before the
SFA
SLRD
T=1
t
WRpwl
T=2
N+1
N
t
SFD
SLOE
T=3
t
N+1
FDH
t
WRpwh
Not Driven
N+1
T=4
■
The same sequence of events is also shown for a burst read
marked with T = 0 through 5.
Note: In burst read mode, during SLOE is assertion, the data bus
is in a driven state and outputs the previous data. Once SLRD is
asserted, the data from the FIFO is driven on the data bus (SLOE
must also be asserted) and then the FIFO pointer is incre-
mented.
The same sequence of events are shown for a burst write and is
indicated by the timing marks of T = 0 through 5.
Note: In the burst write mode, once SLWR is deasserted, the
data is written to the FIFO and then the FIFO pointer is incre-
mented to the next byte in the FIFO. The FIFO pointer is post
incremented.
In
SLWR is deasserted, the short 4-byte packet can be committed
to the host using the PKTEND. The external device should be
designed to not assert SLWR and the PKTEND signal at the
same time. It should be designed to assert the PKTEND after
SLWR is deasserted and met the minimum de-asserted pulse
width. The FIFOADDR lines are to be held constant during the
PKTEND assertion.
t
WRpwl
SLOE
The data that is driven, after asserting SLRD, is the updated
data from the FIFO. This data is valid after a propagation delay
of t
N is the first valid data read from the FIFO. For data to appear
on the data bus during the read cycle (that is, SLRD is
asserted), SLOE MUST be in an asserted state. SLRD and
SLOE can also be tied together.
T=5
The FIFO flag is also updated after t
edge of SLWR.
Figure 13-21.
t
SFD
XFD
T=6
N+1
t
N+2
FDH
N
t
WRpwh
from the activating edge of SLRD. In
SLRD
T=7
N+1
N+1
t
once the four bytes are written to the FIFO and
WRpwl
T=8
SLRD
t
SFD
T=9
t
t
N+3
WRpwh
FDH
N+2
N+1
SLRD
N+2
N+2
SLRD
t
XFLG
PEpwl
[13]
N+3
N+2
from the deasserting
t
CY7C68001
XFLG
Figure
t
PEpwh
t
FAH
Page 36 of 45
SLOE
13-21., data
Not Driven
N+3
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