CY7C68001-56LFXC Cypress Semiconductor Corp, CY7C68001-56LFXC Datasheet - Page 32

• Manufacturer Part Number: CY7C68001-56LFXC
• Description: IC,Bus Controller,LLCC,56PIN
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr
• Type: USBr

Specifications of CY7C68001-56LFXC

• Protocol: USB 2.0
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 56-VQFN Exposed Pad, 56-HVQFN, 56-SQFN, 56-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 428-1942; CY7C68001-56LFXC

Table 13-16. Slave FIFO Asynchronous Packet End Strobe Parameters
Table 13-17. Slave FIFO Asynchronous Address Parameters
13.1 Slave FIFO Address to Flags/Data
Following timing is applicable to synchronous and asynchronous interfaces.
Table 13-18. Slave FIFO Address to Flags/Data Parameters
Document #: 38-08013 Rev. *J
t
t
t
t
t
t
t
t
PEpwl
PWpwh
XFLG
SFA
FAH
FAH
XFLG
XFD
Note
15. Slave FIFO asynchronous parameter values are using internal IFCLK setting at 48 MHz.
Parameter
Parameter
Parameter
PKTEND Pulse Width LOW
PKTEND Pulse Width HIGH
PKTEND to FLAGS Output Propagation Delay
FIFOADR[2:0] to RD/WR/PKTEND Setup Time
SLRD/PKTEND to FIFOADR[2:0] Hold Time
SLWR to FIFOADR[2:0] Hold Time
FIFOADR[2:0] to FLAGS Output Propagation Delay
FIFOADR[2:0] to FIFODATA Output Propagation Delay
Figure 13-12. Slave FIFO Asynchronous Packet End Strobe Timing Diagram
SLCS/FIFOADR[2:0]
SLRD/SLWR/PKTEND
Figure 13-13. Slave FIFO Asynchronous Address Timing Diagram
Figure 13-14. Slave FIFO Address to Flags/Data Timing Diagram
FIFOADR [2.0]
PKTEND
FLAGS
FLAGS
DATA
Description
Description
Description
t
SFA
t
PEpwl
t
XFLG
[15]
t
XFLG
t
XFD
N
t
PEpwh
[15]
N+1
t
FAH
Min
Min
Min
50
50
10
20
70
Max
Max
Max
10.7
14.3
[12]
110
[13]
CY7C68001
Unit
Unit
Unit
ns
ns
ns
ns
ns
ns
ns
ns
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