CY7C68001-56LFXC Cypress Semiconductor Corp, CY7C68001-56LFXC Datasheet - Page 35

• Manufacturer Part Number: CY7C68001-56LFXC
• Description: IC,Bus Controller,LLCC,56PIN
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr
• Type: USBr

Specifications of CY7C68001-56LFXC

• Protocol: USB 2.0
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 56-VQFN Exposed Pad, 56-HVQFN, 56-SQFN, 56-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 428-1942; CY7C68001-56LFXC

Figure 13-18.
signals during a synchronous write using IFCLK as the synchro-
nizing clock. The diagram illustrates a single write followed by
burst write of 3 bytes and committing all 4 bytes as a short packet
using the PKTEND pin.
■
■
■
The same sequence of events are also shown for a burst write
and are marked with the time indicators of T = 0 through 5. Note:
For the burst mode, SLWR and SLCS are left asserted for the
entire duration of writing all the required data values. In this burst
write mode, after the SLWR is asserted, the data on the FIFO
Document #: 38-08013 Rev. *J
• While the SLWR is asserted, data is written to the FIFO and
At t = 0 the FIFO address is stable and the signal SLCS is
asserted. (SLCS may be tied low in some applications)
Note: t
is running at 48 MHz, the FIFO address setup time is more than
one IFCLK cycle.
At t = 1, the external master/peripheral must output the data
value onto the data bus with a minimum set up time of t
before the rising edge of IFCLK.
At t = 2, SLWR is asserted. The SLWR must meet the setup
time of t
edge of IFCLK) and maintain a minimum hold time of t
from the IFCLK edge to the de-assertion of the SLWR signal).
If SLCS signal is used, it must be asserted with SLWR or before
SLWR is asserted. (that is, the SLCS and SLWR signals must
both be asserted to start a valid write condition).
on the rising edge of the IFCLK, the FIFO pointer is incre-
mented. The FIFO flag is also updated after a delay of t
from the rising edge of the clock.
FIFOADR
FLAGS
DATA
SLRD
SLCS
SLOE
SFA
SWR
has a minimum of 25 ns. This means when IFCLK
shows the timing relationship of the SLAVE FIFO
(time from asserting the SLWR signal to the rising
t=0
t=1
Driven
Data (X)
t
Figure 13-19. Slave FIFO Asynchronous Read Sequence and Timing Diagram
SFA
t
OEon
t=2
t
RDpwl
t
XFD
t=3
N
t=4
t
RDpwh
t
FAH
t
OEoff
t
XFLG
T=0
T=1
WRH
t
SFD
t
SFA
OEon
(time
XFLG
N
T=2
t
RDpwl
t
XFD
T=3
data bus is written to the FIFO on every rising edge of IFCLK.
The FIFO pointer is updated on each rising edge of IFCLK. As
shown in
FIFO, SLWR is deasserted. The short 4-byte packet can be
committed to the host by asserting the PKTEND signal.
There is no specific timing requirement that needs to be met for
asserting PKTEND signal with regards to asserting the SLWR
signal. PKTEND can be asserted with the last data value or
thereafter. The only consideration is the setup time t
hold time t
number of data values committed includes the last value written
to the FIFO. In this example, both the data value and the
PKTEND signal are clocked on the same rising edge of IFCLK.
PKTEND can be asserted in subsequent clock cycles. The
FIFOADDR lines should be held constant during the PKTEND
assertion.
Although there are no specific timing requirement for the
PKTEND assertion, there is a specific corner case condition that
needs attention while using the PKTEND to commit a one
byte/word packet. Additional timing requirements exists when
the FIFO is configured to operate in auto mode and it is desired
to send two packets: a full packet (full defined as the number of
bytes in the FIFO meeting the level set in AUTOINLEN register)
committed automatically followed by a short one byte/word
packet committed manually using the PKTEND pin. In this case,
the external master must make sure to assert the PKTEND pin
at least one clock cycle after the rising edge that caused the last
byte/word to be clocked into the previous auto committed packet
(the packet with the number of bytes equal to what is set in the
AUTOINLEN register).
t
N+1
RDpwh
T=4
Figure 13-19.
PEH
t
RDpwl
t
XFD
T=5
must be met. In the scenario of
t
N+2
RDpwh
T=6
once the four bytes are written to the
t
RDpwl
t
XFD
N+3
T=7
t
t
RDpwh
FAH
t
OEoff
t
XFLG
CY7C68001
Figure
Page 35 of 45
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13-19., the
and the
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