CY7C68001-56LFXC Cypress Semiconductor Corp, CY7C68001-56LFXC Datasheet - Page 20

• Manufacturer Part Number: CY7C68001-56LFXC
• Description: IC,Bus Controller,LLCC,56PIN
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr
• Type: USBr

Specifications of CY7C68001-56LFXC

• Protocol: USB 2.0
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 56-VQFN Exposed Pad, 56-HVQFN, 56-SQFN, 56-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 428-1942; CY7C68001-56LFXC

9.6 EPxPKTLENH/L Registers 0x0A–0x11
The external master can use these registers to set smaller
packet sizes than the physical buffer size (refer to the previously
described EPxCFG registers). The default packet size is 512
bytes for all endpoints. Note that EP2 and EP6 can have
maximum sizes of 1024 bytes, and EP4 and EP8 can have
maximum sizes of 512 bytes, to be consistent with the endpoint
structure.
In addition, the EPxPKTLENH register has four other endpoint
configuration bits.
9.6.1 Bit 7: INFM1 EPxPKTLENH.7
When the external master sets INFM = 1 in an endpoint config-
uration register, the FIFO flags for that endpoint become valid
one sample earlier than when the full condition occurs. These
bits take effect only when the FIFOs are operating synchronously
according to an internally or externally supplied clock. Having the
FIFO flag indications one sample early simplifies some
synchronous interfaces. This applies only to IN endpoints.
Default is INFM1 = 0.
9.6.2 Bit 6: OEP1 EPxPKTLENH.6
When the external master sets an OEP = 1 in an endpoint config-
uration register, the FIFO flags for that endpoint become valid
one sample earlier than when the empty condition occurs. These
bits take effect only when the FIFOs are operating synchronously
according to an internally or externally supplied clock. Having the
FIFO flag indications one sample early simplifies some
synchronous interfaces. This applies only to OUT endpoints.
Default is OEP1 = 0.
Document #: 38-08013 Rev. *J
EPxPK-
TLENL
Bit #
Bit Name
Read/Write
Default
EP2PKTLE
NH,
EP6PKTLE
NH
Bit #
Bit Name
Read/Write
Default
EP4PKTLEN
H,
EP8PKTLEN
H
Bit #
Bit Name
Read/Write
Default
INFM1 OEP1 ZERO
R/W
PL7
R/W
INFM1 OEP1 ZERO
7
0
R/W
7
0
7
0
R/W
PL6
R/W
6
0
R/W
6
0
6
0
R/W
PL5
LEN
R/W
5
0
5
1
LEN
R/W
5
1
WORD
PL4
R/W
WIDE
R/W
WORD
4
0
WIDE
4
1
R/W
4
1
R/W
PL3
R/W
3
0
3
0
R/W
0
3
0
0
R/W
PL2
PL10
R/W
2
0
2
0
R/W
2
0
0
R/W
PL1
R/W
0x0B, 0x0D,
1
0
PL9
1
1
R/W
0x0F, 0x11
0x0A, 0x0E
PL9
1
1
0x0C, 0x10
R/W
PL0
R/W
PL8
0
0
R/W
PL8
0
0
0
0
9.6.3 Bit 5: ZEROLEN EPxPKTLENH.5
When ZEROLEN = 1 (default), a zero length packet is sent when
the PKTEND pin is asserted and there are no bytes in the current
packet. If ZEROLEN = 0, then a zero length packet is not sent
under these conditions.
9.6.4 Bit 4: WORDWIDE EPxPKTLENH.4
This bit controls whether the data interface is 8 or 16 bits wide.
If WORDWIDE = 0, the data interface is eight bits wide, and
FD[15:8] have no function. If WORDWIDE = 1 (default), the data
interface is 16 bits wide.
9.6.5 Bit [2..0]: PL[X:0] Packet Length Bits
The default packet size is 512 bytes for all endpoints.
9.7 EPxPFH/L Registers 0x12–0x19
The Programmable Flag registers control when the PF goes
active for each of the four endpoint FIFOs: EP2, EP4, EP6, and
EP8. The EPxPFH/L fields are interpreted differently for the high
speed operation and full speed operation and for OUT and IN
endpoints.
Following is the register bit definition for high speed operation
and for full speed operation (when endpoint is configured as an
isochronous endpoint).
Full Speed ISO and High Speed Mode:
EP4PFH, EP8PFH
Full Speed ISO and High Speed Mode:
EP2PFH, EP6PFH
Full Speed ISO and High Speed Mode: EP2PFL,
EP4PFL, EP6PFL, EP8PFL
Bit #
Bit Name
Read/Write
Default
Bit #
Bit Name
Read/Write
Default
Bit #
Bit Name
Read/Write
Default
DECIS PKTSTAT
PFC7 PFC6 PFC5 PFC4 PFC3 PFC2 PFC1 PFC0
DECIS PKTSTAT
R/W
R/W
R/W
7
1
7
0
7
0
R/W
R/W
6
0
6
0
R/W
6
0
R/W
PKTS[2]
5
0
PFC12
OUT:
R/W
R/W
IN:
5
0
5
0
0
R/W
PKTS[1]
4
0
PKTS[1]
PFC10
PFC11
OUT:
R/W
OUT:
R/W
IN:
IN:
4
0
4
0
R/W
3
0
PKTS[0]
PKTS[0]
PFC10
PFC9
OUT:
OUT:
R/W
R/W
IN:
IN:
3
1
3
1
CY7C68001
R/W
2
0
R/W R/W R/W
R/W R/W R/W
2
0
0
2
0
0
Page 20 of 45
R/W
PFC9 PFC8
1
0
0x13, 0x15,
0x12, 0x16
0x17, 0x19
0x14, 0x18
1
0
1
0
0
R/W
PFC8
0
0
0
0
0
0
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