ADSP-2189MBSTZ-266 Analog Devices Inc, ADSP-2189MBSTZ-266 Datasheet - Page 6

• Manufacturer Part Number: ADSP-2189MBSTZ-266
• Description: IC,DSP,16-BIT,CMOS,QFP,100PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: ADSP-21xxr
• Type: Fixed Pointr

Specifications of ADSP-2189MBSTZ-266

• Interface: Host Interface, Serial Port
• Clock Rate: 66MHz
• Non-volatile Memory: External
• On-chip Ram: 192kB
• Voltage - I/o: 3.30V
• Voltage - Core: 2.50V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Device Core Size: 16b
• Format: Fixed Point
• Clock Freq (max): 66MHz
• Mips: 66
• Device Input Clock Speed: 66MHz
• Ram Size: 192KB
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (min): 2.25V
• Operating Supply Voltage (max): 2.75/3.6V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADSP-2189MBSTZ266

ADSP-2189M
faster rate than can be serviced, due to the additional time the
processor takes to come out of the idle state (a maximum of n
processor cycles).
SYSTEM INTERFACE
Figure 2 shows typical basic system configurations with the
ADSP-2189M, two serial devices, a byte-wide EPROM and
optional external program and data overlay memories (mode
selectable). Programmable Wait-State generation allows the
processor connects easily to slow peripheral devices. The
ADSP-2189M also provides four external interrupts and two
serial ports or six external interrupts and one serial port. Host
Memory Mode allows access to the full external data bus, but
limits addressing to a single address bit (A0). Additional system
peripherals can be added in this mode through the use of exter-
nal hardware to generate and latch address signals.
CONTROLLER
INTERFACE
SYSTEM
1/2x CLOCK
1/2x CLOCK
CRYSTAL
CRYSTAL
OR
SERIAL
DEVICE
SERIAL
DEVICE
SERIAL
DEVICE
SERIAL
DEVICE
OR
Figure 2. ADSP-2189M Basic System Interface
OR
16
FL0-2
IRQ2/PF7
IRQE/PF4
IRQL0/PF5
IRQL1/PF6
MODE C/PF2
MODE B/PF1
MODE A/PF0
SCLK1
RFS1 OR IRQ0
TFS1 OR IRQ1
DT1 OR FO
DR1 OR FI
SCLK0
RFS0
TFS0
DT0
DR0
MODE C/PF2
MODE B/PF1
MODE A/PF0
SCLK1
RFS1 OR IRQ0
TFS1 OR IRQ1
DT1 OR FO
DR1 OR FI
SCLK0
RFS0
TFS0
DT0
DR0
IRD/D6
IWR/D7
IS/D4
IAL/D5
IACK/D3
FULL MEMORY MODE
CLKIN
XTAL
MODE D/PF3
HOST MEMORY MODE
CLKIN
MODE D/PF3
IAD15-0
XTAL
FL0-2
IRQ2/PF7
IRQE/PF4
IRQL0/PF5
IRQL1/PF6
IDMA PORT
SPORT1
SPORT0
SPORT0
SPORT1
ADSP-2189M
ADSP-2189M
ADDR13-0
DATA23-0
DATA23-8
PWDACK
PWDACK
IOMS
IOMS
BMS
DMS
CMS
BGH
PWD
PMS
BMS
DMS
CMS
PWD
PMS
BGH
WR
WR
RD
BG
RD
BR
BR
BG
A0
14
1
24
16
A
D
13-0
23-16
D
A
D
A
D
15-8
10-0
23-8
13-0
23-0
A0-A21
CS
ADDR
DATA
CS
ADDR
DATA
DATA
(PERIPHERALS)
2048 LOCATIONS
PM SEGMENTS
DM SEGMENTS
OVERLAY
I/O SPACE
MEMORY
MEMORY
TWO 8K
TWO 8K
BYTE
–6–
Clock Signals
The ADSP-2189M can be clocked by either a crystal or a TTL-
compatible clock signal.
The CLKIN input cannot be halted, changed during operation,
or operated below the specified frequency during normal opera-
tion. The only exception is while the processor is in the power-
down state. For additional information, refer to Chapter 9,
ADSP-2100 Family User’s Manual, Third Edition for detailed
information on this power-down feature.
If an external clock is used, it should be a TTL-compatible
signal running at half the instruction rate. The signal is con-
nected to the processor’s CLKIN input. When an external clock
is used, the XTAL input must be left unconnected.
The ADSP-2189M uses an input clock with a frequency equal
to half the instruction rate; a 37.50 MHz input clock yields a
13.3 ns processor cycle (which is equivalent to 75 MHz). Nor-
mally, instructions are executed in a single processor cycle. All
device timing is relative to the internal instruction clock rate,
which is indicated by the CLKOUT signal when enabled.
Because the ADSP-2189M includes an on-chip oscillator cir-
cuit, an external crystal may be used. The crystal should be
connected across the CLKIN and XTAL pins, with two capaci-
tors connected as shown in Figure 3. Capacitor values are de-
pendent on crystal type and should be specified by the crystal
manufacturer. A parallel-resonant, fundamental frequency,
microprocessor-grade crystal should be used.
A clock output (CLKOUT) signal is generated by the processor
at the processor’s cycle rate. This can be enabled and disabled
by the CLKODIS bit in the SPORT0 Autobuffer Control
Register.
Reset
The RESET signal initiates a master reset of the ADSP-2189M.
The RESET signal must be asserted during the power-up se-
quence to assure proper initialization. RESET during initial
power-up must be held long enough to allow the internal clock
to stabilize. If RESET is activated any time after power-up, the
clock continues to run and does not require stabilization time.
The power-up sequence is defined as the total time required for
the crystal oscillator circuit to stabilize after a valid V
plied to the processor and for the internal phase-locked loop
(PLL) to lock onto the specific crystal frequency. A minimum of
2000 CLKIN cycles ensures that the PLL has locked but does
not include the crystal oscillator start-up time. During this
power-up sequence the RESET signal should be held low. On
any subsequent resets, the RESET signal must meet the mini-
mum pulsewidth specification, t
The RESET input contains some hysteresis; however, if you use
an RC circuit to generate your RESET signal, the use of an
external Schmidt trigger is recommended.
Figure 3. External Crystal Connections
CLKIN
DSP
XTAL
RSP
.
CLKOUT
DD
is ap-
REV. A