AD9864BCPZRL Analog Devices Inc, AD9864BCPZRL Datasheet - Page 35

• Manufacturer Part Number: AD9864BCPZRL
• Description: IC,RF/Baseband Circuit,LLCC,48PIN,PLASTIC
• Manufacturer: Analog Devices Inc

Specifications of AD9864BCPZRL

• Rf Type: UHF, Cellular, GSM, EDGE, TETRA
• Frequency: 10MHz ~ 300MHz
• Features: General Purpose IF Subsystem
• Package / Case: 48-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

data is used, the effective system NF will increase because of the
quantization noise present in the 16-bit data after truncation.
Figure 65 plots the nominal system NF with 16-bit output data
as a function of AGC in both narrow-band and wideband
mode. In wideband mode, the NF curve is virtually unchanged
relative to the 24-bit output data because the output SNR before
truncation is always less than the 96 dB SNR that 16-bit data
can support. However, in narrow-band mode, where the output
SNR approaches or exceeds the SNR that can be supported with
16-bit data, the degradation in system NF is more severe. Fur-
thermore, if the signal processing within the DSP adds noise at
the level of an LSB, the system noise figure can be degraded
even more than Figure 65 shows. For example, this could occur
in a fixed 16-bit DSP whose code is not optimized to process
the AD9864’s 16-bit data with minimal quantization effects. To
limit the quantization effects within the AD9864, the 24-bit
data undergoes noise shaping just prior to 16-bit truncation,
thus reducing the in-band quantization noise by 5 dB (with 2×
oversampling). This explains why 98.8 dBFS SNR performance
is still achievable with 16-bit data in a 10 kHz BW.
Figure 64. Nominal System Noise Figure and Peak SNR vs. AGCG Setting (f
Figure 65. Nominal System Noise Figure and Peak SNR vs. AGCG
15
14
13
12
11
10
17
16
15
14
13
12
11
10
Setting (f
9
8
9
8
0
SNR = 82.9dBFS
0
SNR = 94.1dBFS
73.35 MHz, f
SNR = 83dBFS
SNR = 95.1dBFS
IF
= 73.35 MHz, f
3
3
BW = 150kHz
BW = 150kHz
CLK
VGA ATTENUATION (dB)
VGA ATTENUATION (dB)
= 18 MSPS, and 24-bit I/Q Data)
BW = 50kHz
CLK
= 18 MSPS, and 16-bit I/Q Data)
6
6
BW = 50kHz
BW = 10kHz
BW = 10kHz
SNR = 98.8dBFS
SNR = 90.1dBFS
9
SNR = 89.9dBFS
SNR = 103.2dB
9
12
1
2
Rev. 0 | Page 35 of 44
IF
=
APPLICATIONS CONSIDERATIONS
Frequency Planning
The LO frequency (and/or ADC clock frequency) must be chosen
carefully to prevent known internally generated spurs from mixing
down along with the desired signal, thus degrading the SNR per-
formance. The major sources of spurs in the AD9864 are the ADC
clock and digital circuitry operating at 1/3 of f
frequency (f
which LO (and therefore IF) frequencies are viable.
Many applications have frequency plans that take advantage of
industry-standard IF frequencies due to the large selection of
low cost crystal or SAW filters. If the selected IF frequency and
ADC clock rate result in a problematic spurious component, an
alternative ADC clock rate should be selected by slightly modi-
fying the decimation factor and CLK synthesizer settings (if
used) such that the output sample rate remains the same. Also,
applications requiring a certain degree of tuning range should
take into consideration the location and magnitude of these
spurs when determining the tuning range as well as optimum
IF and ADC clock frequency.
Figure 66 plots the measured in-band noise power as a function
of the LO frequency for f
bandwidth of 150 kHz when no signal is present. Any LO
frequency resulting in large spurs should be avoided. As this
figure shows, large spurs result when the LO is f
MHz away from a harmonic of 18 MHz , i.e., n f
Also problematic are LO frequencies whose odd order harmon-
ics, i.e., m f
mechanism is a result of the mixer being internally driven
by a squared-up version of the LO input consisting of the LO
frequency and its odd order harmonics. These spur frequencies
can be calculated from the relation
where m = 1, 3, 5... and n = 1, 2, 3...
A second source of spurs is a large block of digital circuitry that
is clocked at f
this spur source are given by
where n = 1, 2, 3...
Figure 67 shows that omitting the LO frequencies given by
Equation 12 for m = 1, 3, and 5 and by Equation 13 accounts
for most of the spurs. Some of the remaining low level spurs
can be attributed to coupling from the SSI digital output. As a
result, users are also advised to optimize the output bit rate
(f
strength to achieve the lowest spurious and noise figure per-
formance for a particular LO frequency and f
especially the case for particularly narrow-band channels in
CLKOUT
m
f
LO
×
via the SSIORD register) and the digital output driver
f
=
LO
LO
CLK
f
CLK
, mix with harmonics of f
=
CLK
) is the most important variable in determining
(
n
/3. Problematic LO frequencies associated with
3 /
±
1
+
8 /
n
×
)
×
f
CLK
CLK
f
CLK
= 18 MHz and an output signal
±
f
CLK
8 /
CLK
to f
CLK
CLK
CLK
. Thus, the clock
/8. This spur
CLK
CLK
setting. This is
/8 = 2.25
± f
AD9864
CLK
/8.
(12)
(13)