AD9864BCPZRL Analog Devices Inc, AD9864BCPZRL Datasheet - Page 18

• Manufacturer Part Number: AD9864BCPZRL
• Description: IC,RF/Baseband Circuit,LLCC,48PIN,PLASTIC
• Manufacturer: Analog Devices Inc

Specifications of AD9864BCPZRL

• Rf Type: UHF, Cellular, GSM, EDGE, TETRA
• Frequency: 10MHz ~ 300MHz
• Features: General Purpose IF Subsystem
• Package / Case: 48-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9864
SYNCHRONOUS SERIAL INTERFACE (SSI)
The AD9864 provides a high degree of programmability of its
SSI output data format, control signals, and timing parameters
to accommodate various digital interfaces. In a 3-wire digital
interface, the AD9864 provides a frame sync signal (FS), a clock
output (CLKOUT), and a serial data stream (DOUTA) signal to
the host device. In a 2-wire interface, the frame sync informa-
tion is embedded into the data stream, thus only CLKOUT and
DOUTA output signals are provided to the host device. The SSI
control registers are SSICRA, SSICRB, and SSIORD. Table 8
shows the different bit fields associated with these registers.
The primary output of the AD9864 is the converted I and Q
demodulated signal available from the SSI port as a serial bit
stream contained within a frame. The output frame rate is equal
to the modulator clock frequency (f
filter’s decimation factor that is programmed in the Decimator
Register (0x07). The bit stream consists of an I word followed
by a Q word, where each word is either 24 bits or 16 bits long
and is given MSB first in twos complement form. Two optional
bytes may also be included within the SSI frame following the
Q word. One byte contains the AGC attenuation and the other
byte contains both a count of modulator reset events and an
estimate of the received signal amplitude (relative to full scale
of the AD9864’s ADC). Figure 31 illustrates the structure of the
SSI data frames in a number of SSI modes.
The two optional bytes are output if the EAGC bit of SSICRA is
set. The first byte contains the 8-bit attenuation setting (0 = no
attenuation, 255 = 24 dB of attenuation), while the second byte
contains a 2-bit reset field and 6-bit received signal strength
field. The reset field contains the number of modulator reset
events since the last report, saturating at 3. The received signal
strength (RSSI) field is a linear estimate of the signal strength at
the output of the first decimation stage; 60 corresponds to a
full-scale signal.
The two optional bytes follow the I and Q data as a 16-bit word
provided that the AAGC bit of SSICRA is not set. If the AAGC
bit is set, the two bytes follow the I and Q data in an alternating
DOUTB
PE
PC
PD
DON'T
CARE
T
t
DS
CLK
) divided by the digital
t
S
DON'T
CARE
R/W
t
HI
t
t
DH
CLK
t
LOW
DON'T
CARE
Figure 30. SPI Read Operation Timing
A5
A1
Rev. 0 | Page 18 of 44
DON'T
CARE
A0
t
DV
DON'T
DON'T
fashion. In this alternate AGC data mode, the LSB of the byte
containing the AGC attenuation is a 0, while the LSB of the
byte containing reset and RSSI information is always a 1.
In a 2-wire interface, the embedded frame sync bit (EFS) within
the SSICRA register is set to 1. In this mode, the framing
information is embedded in the data stream, with each eight
bits of data surrounded by a start bit (low) and a stop bit (high),
and each frame ends with at least 10 high bits. FS remains
either low or three-stated (default), depending on the state of
the SFST bit. Other control bits can be used to invert the frame
sync (SFSI), to delay the frame sync pulse by one clock period
(SLFS), to invert the clock (SCKI), or to three-state the clock
(SCKT). Note that if EFS is set, SLFS is a Don’t Care.
The SSIORD register controls the output bit rate (f
serial bit stream. f
frequency (f
divided by the contents of the SSIORD register. Note that f
should be chosen such that it does not introduce harmful spurs
within the pass band of the target signal. Users must verify that
the output bit rate is sufficient to accommodate the required
number of bits per frame for a selected word size and decimation
factor. Idle (high) bits are used to fill out each frame.
CARE
CARE
24-BIT I AND Q, EAGC = 0, AAGC = X:48 DATA BITS
24-BIT I AND Q, EAGC = 1, AAGC = 0:64 DATA BITS
16-BIT I AND Q, EAGC = 0, AAGC = X:32 DATA BITS
16-BIT I AND Q, EAGC = 0, AAGC = 0:32 DATA BITS
16-BIT I AND Q, EAGC = 1, AAGC = 1:40 DATA BITS
I(15:0)
I(15:0)
I(15:0)
I(15:0)
I(23:0)
I(23:0)
D7
D7
CLK
) or an integer fraction of it. It is equal to f
RESET COUNT
CLKOUT
D6
D6
Figure 31. SSI Frame Structure
Q(15:0)
Q(15:0)
Q(15:0)
Q(15:0)
can be set equal to the modulator clock
D1
D1
t
EZ
ATTN(7:1)
ATTN(7:0)
Q(23:0)
Q(23:0)
D0
D0
SSI(5:1)
0
1
DON'T
CARE
SSI(5:0)
RESET COUNT
ATTN(7:0)
CLKOUT
) of the
CLK
SSI(5:0)
CLKOUT