AD9864BCPZRL Analog Devices Inc, AD9864BCPZRL Datasheet - Page 28

• Manufacturer Part Number: AD9864BCPZRL
• Description: IC,RF/Baseband Circuit,LLCC,48PIN,PLASTIC
• Manufacturer: Analog Devices Inc

Specifications of AD9864BCPZRL

• Rf Type: UHF, Cellular, GSM, EDGE, TETRA
• Frequency: 10MHz ~ 300MHz
• Features: General Purpose IF Subsystem
• Package / Case: 48-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9864
Figure 49 shows the nominal signal transfer function magni-
tude for frequencies near the f
pass band determines the transfer function droop, but even at
the lowest oversampling ratio (48) where the pass band edges
are at ±f
0.5 dB. Note that the amount of attenuation offered by the sig-
nal transfer function near f
determining the narrow-band IF filtering requirements preced-
ing the AD9864.
Tuning of the Σ-∆ modulator’s two continuous-time resonators
is essential in realizing the ADC’s full dynamic range and must
be performed upon system startup. To facilitate tuning of the
LC tank, a capacitor array is internally connected to the MXOP
and MXON pins. The capacitance of this array is programmable
from 0 pF to 200 pF ± 20% and can be programmed either
automatically or manually via the SPI port. The capacitors of
the active RC resonator are similarly programmable. Note that
the AD9864 can be placed in and out of its standby mode with-
out retuning since the tuning codes are stored in the SPI Registers.
Figure 49. Magnitude of the ADC’s Signal Transfer Function near f
–10
–20
–30
–40
–50
–60
–70
–80
–10
–15
–20
–5
0
0
–0.10
0
CLK
Figure 48. Signal Transfer Function of the Band-Pass Σ-∆
/192 (±0.005 f
NORMALIZED FREQUENCY (RELATIVE TO
NORMALIZED FREQUENCY (RELATIVE TO
–0.05
0.5
Modulator from 0 f
NOTCH AT ALL ALIAS FREQUENCIES
CLK
CLK
), the gain variation is less than
/8 should also be considered when
CLK
1.0
0
/8 pass band. The width of the
CLK
to 2f
CLK
1.5
0.05
f
OUT
f
CLK
)
)
0.10
2.0
CLK
/8
Rev. 0 | Page 28 of 44
When tuning the LC tank, the sampling clock frequency must
be stable and the LNA/mixer, LO synthesizer, and ADC must
all be placed in standby. Large LO and IF signals present at the
inputs of the AD9864 can corrupt the calibration. These signals
should be minimized or disabled during the calibration
sequence. Tuning is triggered when the ADC is taken out of
standby if the TUNE_LC bit of Register 0x1C has been set. This
bit will clear when the tuning operation is complete (less than
6 ms). The tuning codes can be read from the 3-bit CAPL1
(0x1D) and the 6-bit CAPL0 (0x1E) registers.
In a similar manner, tuning of the RC resonator is activated if
the TUNE_RC bit of Register 0x1C is set when the ADC is
taken out of standby. This bit will clear when tuning is com-
plete. The tuning code can be read from the CAPR (0x1F)
register. Setting both the TUNE_LC and TUNE_RC bits tunes
the LC tank and the active RC resonator in succession. During
tuning, the ADC is not operational and neither data nor a clock
is available from the SSI port. Table 15 lists the recommended
sequence of the SPI commands for tuning the ADC, and
Table 16 lists all of the SPI registers associated with band-pass
Σ-∆ ADC.
Table 15. Tuning Sequence
Address (Hex)
0x00
0x1C
0x00
*If external CLK VCO or source used, the CLK oscillator must also be disabled.
Table 16. SPI Registers Associated with Band-Pass Σ-∆ ADC
Address
(Hex)
0x00
0x1C
0x1D
0x1E
0x1F
Once the AD9864 has been tuned, the noise figure degradation
attributed solely to the temperature drift of the LC and RC
resonators is minimal. Since the drift of the RC resonator is
actually negligible compared to that of the LC resonator, the
external L and C components’ temperature drift characteristics
tend to dominate. Figure 50 shows the degradation in noise
figure as the product of the LC value is allowed to vary from
–12.5% to +12.5%. Note that the noise figure remains relatively
Large IF or LO signals can corrupt the calibration; these signals should be
disabled during the calibration sequence.
Value
(7:0)
(1)
(0)
(2:0)
(5:0)
(7:0)
Value
0x45
0x03
0x44
Width
8
1
1
3
6
8
Comments
LO synthesizer, LNA/mixer, and
ADC are placed in standby.*
Set TUNE_LC and TUNE_RC. Wait
for CLK to stabilize if CLK
synthesizer used.
Take the ADC out of standby. Wait
for 0x1C to clear (<6 ms).
LNA/mixer can now be taken out
of standby
Default
Value
0xFF
0
0
0
0x00
0x00
Name
STBY
TUNE_LC
TUNE_RC
CAPL1 (2:0)
CAPL1 (5:0)
CAPR