AD9864BCPZRL Analog Devices Inc, AD9864BCPZRL Datasheet - Page 15

• Manufacturer Part Number: AD9864BCPZRL
• Description: IC,RF/Baseband Circuit,LLCC,48PIN,PLASTIC
• Manufacturer: Analog Devices Inc

Specifications of AD9864BCPZRL

• Rf Type: UHF, Cellular, GSM, EDGE, TETRA
• Frequency: 10MHz ~ 300MHz
• Features: General Purpose IF Subsystem
• Package / Case: 48-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SERIAL PERIPHERAL INTERFACE (SPI)
The SPI is a bidirectional serial port. It is used to load the configuration information into the registers listed below as well as to read back
their contents. Table 6 provides a list of the registers that can be programmed through the SPI port. Addresses and default values are given
in hexadecimal form.
Table 6. SPI Address Map
Address (Hex)
POWER CONTROL REGISTERS
0x00
0x01
0x02
AGC
0x03
0x04
0x05
0x06
DECIMATION FACTOR
0x07
LO SYNTHESIZER
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
CLOCK SYNTHESIZER
0x10
0x11
0x12
Bit
Breakdown
(7:0)
(3:2)
(1:0)
(7:0)
(7)
(6:0)
(7:0)
(7:4)
(3:0)
(7)
(6:4)
(3)
(2:0)
(7:5)
(4)
(3:0)
(5:0)
(7:0)
(7:5)
(4:0)
(7:0)
(6)
(5)
(4:2)
(1:0)
(5:0)
(7:0)
(5:0)
(7:0)
(4:0)
Width
8
2
2
8
1
7
8
4
4
1
3
1
3
3
1
4
6
8
3
5
8
1
1
3
2
6
8
6
8
5
Default
Value
0xFF
0x00
0x00
0x00
0
0x00
0x00
0x00
0x00
0
0x00
0
0x00
0
0x04
0x00
0x38
0x05
0x00
0x1D
0
0
0x00
0x03
0x00
0x04
0x00
0x38
0x00
Name
STBY
CKOB
ADCB
TEST
ATTEN
AGCG (14:8)
AGCG (7:0)
AGCA
AGCD
AGCV
AGCO
AGCF
AGCR
Unused
K
M
LOR (13:8)
LOR (7:0)
LOA
LOB (12:8)
LOB (7:0)
LOF
LOINV
LOI
LOTM
LOFA (13:8)
LOFA (7:0)
CKR (13:8)
CKR (7:0)
CKN (12:8)
Rev. 0 | Page 15 of 44
Description
Standby control bits (REF, LO, CKO, CK, GC, LNAMX, unused, and
ADC). Default is power-up condition of standby.
CK oscillator bias (0 = 0.25 mA, 1 = 0.35 mA, 2 = 0.40 mA,
3 = 0.65 mA).
Do not use.
Factory test mode. Do not use.
Apply 16 dB attenuation in the front end.
AGC attenuation setting (7 MSBs of a 15-bit unsigned word).
AGC attenuation setting (8 LSBs of a 15-bit unsigned word).
AGC attack bandwidth setting. Default yields 50 Hz loop
bandwidth.
AGC decay time setting. Default is decay time = attack time.
Enable digital VGA to increase AGC range by 12 dB.
AGC overload update setting. Default is slowest update.
Fast AGC (minimizes resistance seen between GCP and GCN).
AGC enable/reference level (disabled, 3 dB, 6 dB, 9 dB, 12 dB,
15 dB below clip).
Decimation factor = 60 × (M + 1), if K = 0; 48 × (M + 1), if K = 1.
Default is decimate-by-300.
Reference frequency divider (6 MSBs of a 14-bit word).
Reference frequency divisor (8 LSBs of a 14-bit word).
Default (56) yields 300 kHz from f
A Counter (prescaler control counter).
B Counter MSB (5 MSB of a 13-bit word).
Default LOA and LOB values yield 300 kHz from 73.35 MHz to
2.25 MHz.
B Counter LSB (8 LSB of a 13-bit word).
Enable fast acquire.
Invert charge pump (0 = source current to increase VCO
frequency).
Charge pump current in normal operation.
I
Manual control of LO charge pump (0 = Off, 1 = Up, 2 = Down,
and 3 = Normal).
LO fast acquire time unit (6 MSBs of a 14-bit word).
LO fast acquire time unit (8 LSBs of a 14-bit word).
Reference frequency divisor (6 MSBs of a 14-bit word).
Reference frequency divisor (8 LSBs of a 14-bit word).
Default yields 300 kHz from f
Maximum = 16383.
Synthesized frequency divisor (5 MSBs of a 13-bit word).
PUMP
= (LOI +1) × 0.625 mA.
REF
= 16.8 MHz; Minimum = 3,
REF
= 16.8 MHz.
AD9864